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US4665506A Expired / Lapsed US ⏱️ 0.0 years remaining

Memory system with write protection

Assignee: Texas Instruments Inc
•
Filing: 1983-01-03
•
Granted: 1987-05-12
•
Expires: 2003-01-03
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Abstract

Abstract A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of the storage elements to a plurality of data lines. Protection circuitry is provided that is connected to the address lines for storing flags corresponding to selected groups of the storage elements to be protected. Write circuitry is provided that is connected to the address lines and to the array of storage elements for preventing the writing into the storage elements addressed by the address lines when the address is within the address of the protected groups. Control circuitry is provided that is connected to the protect circuit and the write circuit for controlling the input of the protect group addresses and for enabling the write circuit means during a write operation. The memory apparatus further includes the capability to provide protection from writing from a direct memory access source or from a central processing unit source. The control circuit in the memory system is provided with an override capability to override the write protection circuits.

Inventors

  • 👤 James H. Cline
  • 👤 David M. Chastain

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 14:41
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/20

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 120 words
A memory apparatus comprising: an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of storage elements to a plurality of data lines; protect circuit means connected to the address lines for storing the address of protected groups of the storage elements; write circuit means connected to the address lines and the array of storage elements for preventing the writing of data into protected groups of storage elements; and control circuit means connected to the protect circuit means and the write circuit means for causing the protected group addresses to be stored in the protect circuit means prior to a write operation and for enabling the write circuit means during a write operation.
Claim 2
Dependent Claim 120 words
A memory apparatus comprising: an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of storage elements to a plurality of data lines; protect circuit means connected to the address lines for storing the address of protected groups of the storage elements; write circuit means connected to the address lines and the array of storage elements for preventing the writing of data into protected groups of storage elements; and control circuit means connected to the protect circuit means and the write circuit means for causing the protected group addresses to be stored in the protect circuit means prior to a write operation and for enabling the write circuit means during a write operation.
Claim 3
Dependent Claim 31 words
A memory apparatus according to claim 1, wherein said protect circuit means includes programmable means for storing blocks of addresses representing the addresses of the protected groups of the storage elements.
Claim 4
Dependent Claim 38 words
A memory apparatus according to claim 2, wherein said protect circuit means further includes means to determine the source of the data to be written into the array and means to restrict the write operations from selected sources.
Claim 5
Dependent Claim 35 words
A memory apparatus according to claim 3, wherein said control circuit means includes an override capability to provide for a write operation into protected groups of the storage elements in spite of their protected status.
Claim 6
Dependent Claim 33 words
A memory apparatus according to claim 4, wherein said write circuit means includes an output means to provide an output when a write operation is attempted into a protected group of storage elements.
Claim 7
Dependent Claim 30 words
A memory apparatus according to claim 5, wherein said control circuit means includes the capability to provide an output when said protect circuit means receives the protected group of addresses.
Claim 8
Dependent Claim 49 words
A memory apparatus according to claim 6, wherein said control circuit means includes a plurality of input signals to determine the status of the override capability and to determine when protected group addresses are input and to determine when the write circuit means is enabled during a write operation.

References Cited (Backward Citations)

US4453236A Cited
US4398269A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-05-11 1990-11-10 1991-05-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-05-11 1994-11-10 1995-05-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-05-11 1998-11-10 1999-05-12 $7700.00 Window Closed / Lapsed

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