Memory with I/O mappable redundant columns

Claim 1

A memory, comprising: an array of memory cells arranged in a plurality of rows and columns, said columns being arranged in a plurality of subarrays; a plurality of column decoder circuits, each said column decoder circuit selecting a single column out of the columns in said subarray in response to a column address signal; a plurality of redundant columns; a redundant column decoder for selecting a single redundant column in response to at least a portion of said column address signal; an input buffer and an output buffer for each of said subarrays, each input buffer and output buffer being connectable to a said column in said subarray; a plurality of switching means, each switching means coupling a said input and a said output buffer either to a selected column in response to first control signals or to a selected redundant column in response to second control signals; and a control circuit for storing the addresses of defective columns and information identifying the input and output buffers capable of coupling each defective column, said control circuit supplying first control signals to all of said switching means when a received column address signal does not match a stored address and supplying second control signals to said switching means capable of coupling each said defective column and first control signals to the remaining switching means when a received column address matches a stored address.