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US5280449A
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Data memory and method of reading a data memory
Assignee: ARM Ltd
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Filing: 1992-10-13
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Granted: 1994-01-18
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Expires: 2012-10-13
Abstract
Abstract A data memory and a method of reading a data memory are described. Data words (Word0, Word1, Word2, Word3) are stored within the data memory within an array of memory cells arranged in columns and rows. A particular data word within a memory cell is accessed by activating a complete row (2) to output the data words within all columns of that row and then selecting the data word from the appropriate column with a data word selection multiplexer (6). An amplifier (8) is used to reduce the time taken for data signals read from the array to reach readable values. In order to save power, the amplifier is disabled during a second and subsequent successive reading operations from a row that has already been activated. Precharging of a output lines is also disabled for second and subsequent successive readings from a row.
Inventors
- 👤 Harry E. Oldham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:58
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
211 words
A data memory for storing a plurality of data words, said data memory comprising: (i) an array of memory cells having a plurality of columns of memory cells and a plurality of rows of memory cells, each of said memory cells being operable to store a data word; (ii) a plurality of column data word output paths each associated with one of said columns of memory cells; (iii) means for coupling data signals representing data words stored within a selected row to said column data word output paths; (iv) a data word selection multiplexer for selecting data signals representing a selected data word on one of said column data word output paths as a selected data word for output from said data memory; (v) an amplifier for amplifying data signals of at least said selected data word so as more rapidly to reach readable values; (vi) means for detecting if successive data words to be read from said data memory are stored in one row of memory cells; and (vii) means, responsive to said means for detecting, for disabling operation of said amplifier and selecting an alternative path for reading data words from said data memory for a second and subsequent successive reading operations from said one row of memory cells.
Claim 2
Dependent Claim
211 words
A data memory for storing a plurality of data words, said data memory comprising: (i) an array of memory cells having a plurality of columns of memory cells and a plurality of rows of memory cells, each of said memory cells being operable to store a data word; (ii) a plurality of column data word output paths each associated with one of said columns of memory cells; (iii) means for coupling data signals representing data words stored within a selected row to said column data word output paths; (iv) a data word selection multiplexer for selecting data signals representing a selected data word on one of said column data word output paths as a selected data word for output from said data memory; (v) an amplifier for amplifying data signals of at least said selected data word so as more rapidly to reach readable values; (vi) means for detecting if successive data words to be read from said data memory are stored in one row of memory cells; and (vii) means, responsive to said means for detecting, for disabling operation of said amplifier and selecting an alternative path for reading data words from said data memory for a second and subsequent successive reading operations from said one row of memory cells.
Claim 3
Dependent Claim
50 words
A data memory as claimed in claim 1, comprising: a precharge circuit for precharging said column data word output paths; and means responsive to said means for detecting for disabling operation of said precharge circuit for a second and subsequent successive reading operations from said one row of memory cells.
Claim 4
Dependent Claim
36 words
A data memory as claimed in claim 1, wherein each of said column data word output paths has two complementary signal lines for each bit of said data word and said amplifier is a differential amplifier.
Claim 5
Dependent Claim
20 words
A data memory as claimed in claim 1, wherein said amplifier is connected downstream of said data word selection multiplexer.
Claim 6
Dependent Claim
52 words
A data memory as claimed in claim 1, wherein said means for disabling and selecting comprises a bypass multiplexer for selecting for output from said data memory one of data signals downstream of said amplifier and data signals upstream of said amplifier and means for interrupting a power supply to said amplifier.
Claim 7
Dependent Claim
60 words
A data memory as claimed in claim 1, wherein each data word has an associated memory address, a higher bit order portion of said memory address identifying a row of memory cells in which said data word is stored and a lower bit order portion identifying a particular data word within said row and controlling said data word selection multiplexer.
Claim 8
Dependent Claim
64 words
A data memory as claimed in claim 6, wherein said data memory is a cache data memory and comprising means for comparing said higher bit order portion of a data word to be read with higher bit order portions of data words stored within rows of memory cells to detect if said data word to be read is present in said cache data memory.
Claim 9
Dependent Claim
44 words
A data memory as claimed in claim 6, wherein said means for detecting detects whether said higher bit order portion of successive data words to be read are identical indicating that said successive data words are stored in said one row of memory cells.
Claim 10
Independent Claim
200 words
A method of reading data words from a data memory comprising: an array of memory cells having a plurality of columns of memory cells and a plurality of rows of memory cells, each of said memory cells being operable to store a data word; a plurality of column data word output paths each associated with one of said columns of memory cells; said method comprising the steps of: (i) coupling data signals representing data words stored within a selected row to said column data word output paths; (ii) selecting data signals representing a selected data word on one of said column data word output paths as a selected data word for output from said data memory; (iii) amplifying data signals of at least said selected data word so as more rapidly to reach readable values; (iv) detecting if successive data words to be read from said data memory are stored in one row of memory cells; and (v) disabling operation of an amplifier for said amplifying step and selecting an alternative path for reading data words from said data memory for a second and subsequent successive reading operations from said one row of memory cells, in response to said detection.
Claim 11
Independent Claim
200 words
A method of reading data words from a data memory comprising: an array of memory cells having a plurality of columns of memory cells and a plurality of rows of memory cells, each of said memory cells being operable to store a data word; a plurality of column data word output paths each associated with one of said columns of memory cells; said method comprising the steps of: (i) coupling data signals representing data words stored within a selected row to said column data word output paths; (ii) selecting data signals representing a selected data word on one of said column data word output paths as a selected data word for output from said data memory; (iii) amplifying data signals of at least said selected data word so as more rapidly to reach readable values; (iv) detecting if successive data words to be read from said data memory are stored in one row of memory cells; and (v) disabling operation of an amplifier for said amplifying step and selecting an alternative path for reading data words from said data memory for a second and subsequent successive reading operations from said one row of memory cells, in response to said detection.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-17 | 1997-07-19 | 1998-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-17 | 2001-07-19 | 2002-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-17 | 2005-07-19 | 2006-01-18 | $7700.00 | Window Closed / Lapsed |