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US5689720A
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High-performance superscalar-based computer system with out-of-order instruction execution
Assignee: Seiko Epson Corp
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Filing: 1996-02-15
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Granted: 1997-11-18
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Expires: 2016-02-15
Abstract
Abstract A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instruction sets and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers which are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
Inventors
- 👤 Le Trong Nguyen
- 👤 Derek J. Lentz
- 👤 Yoshiyuki Miyayama
- 👤 Sanjiv Garg
- 👤 Yasuaki Hagiwara
- 👤 Johannes Wang
- 👤 Te-Li Lau
- 👤 Sze-Shun Wang
- 👤 Quang H. Trang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:29
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3818; G06F9/3822; G06F9/30003; G06F9/3005; G06F9/30054; G06F9/30061; G06F9/30072; G06F9/30098; G06F9/30105; G06F9/30112; G06F9/30116; G06F9/3012; G06F9/30123; G06F9/3013; G06F9/30134; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/32; G06F9/322; G06F9/323; G06F9/327; G06F9/3802; G06F9/3804; G06F9/3806; G06F9/3824; G06F9/3826; G06F9/3834; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3851; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/3861; G06F9/3863; G06F9/3865; G06F9/3885
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
116 words
A superscalar microprocessor, comprising: means for storing data in a plurality of registers identifiable by register references, said plurality of registers including a predetermined register and a temporary register, wherein said temporary register is configured for storing out-of-order execution results; means for fetching a predetermined sequence of instructions to be executed, wherein an instruction of said predetermined sequence of instructions includes a register reference; and executing means, coupled to said fetching means, for executing said instructions out of said predetermined sequence, said executing means including means, coupled to said storing means, for selecting said temporary register where the execution of said instruction provides said register reference to select said predetermined register for the storage of data.
Claim 2
Dependent Claim
116 words
A superscalar microprocessor, comprising: means for storing data in a plurality of registers identifiable by register references, said plurality of registers including a predetermined register and a temporary register, wherein said temporary register is configured for storing out-of-order execution results; means for fetching a predetermined sequence of instructions to be executed, wherein an instruction of said predetermined sequence of instructions includes a register reference; and executing means, coupled to said fetching means, for executing said instructions out of said predetermined sequence, said executing means including means, coupled to said storing means, for selecting said temporary register where the execution of said instruction provides said register reference to select said predetermined register for the storage of data.
Claim 3
Dependent Claim
57 words
The microprocessor according to claim 1, wherein: said executing means further includes: means for determining whether all instructions in said predetermined sequence of instructions prior to said instruction have been executed and means, responsive to said determining means and coupled to said storing means, for transferring the data stored by said temporary register to said predetermined register.
Claim 4
Dependent Claim
258 words
A computer system, comprising: a main memory bus; input/output bus; and means for processing instructions, operably coupled with said main memory bus and said input/output bus, said processing means including: means for obtaining instructions to be executed over said main memory bus, wherein said instructions having a predetermined program order and one of said instructions includes a register reference, means for storing respective data in a plurality of registers including a predetermined register and a temporary register, wherein said temporary register is configured for storing out-of-order execution results, means for executing said instructions via one of a plurality of functional unit means, wherein said executing means is operably coupled with said obtaining means, said executing means including means for directing the storage of data by said one instruction to said temporary register, wherein said register reference is said predetermined register and said one instruction is executed out of said predetermined program order, and means for retiring said executed instructions in said predetermined program order; and bus means for providing plural data routing paths between said one of predetermined register and said temporary register, and said plurality of functional unit means; and means for controlling the operation of said bus means to transfer data between one of said predetermined register and said temporary register, and said plurality of functional unit means; wherein said means for controlling provides for concurrent execution of said instructions, said controlling means controlling the initiation of said concurrent execution of instructions based on the availability of said functional unit means for the processing of data.
Claim 5
Dependent Claim
258 words
A computer system, comprising: a main memory bus; input/output bus; and means for processing instructions, operably coupled with said main memory bus and said input/output bus, said processing means including: means for obtaining instructions to be executed over said main memory bus, wherein said instructions having a predetermined program order and one of said instructions includes a register reference, means for storing respective data in a plurality of registers including a predetermined register and a temporary register, wherein said temporary register is configured for storing out-of-order execution results, means for executing said instructions via one of a plurality of functional unit means, wherein said executing means is operably coupled with said obtaining means, said executing means including means for directing the storage of data by said one instruction to said temporary register, wherein said register reference is said predetermined register and said one instruction is executed out of said predetermined program order, and means for retiring said executed instructions in said predetermined program order; and bus means for providing plural data routing paths between said one of predetermined register and said temporary register, and said plurality of functional unit means; and means for controlling the operation of said bus means to transfer data between one of said predetermined register and said temporary register, and said plurality of functional unit means; wherein said means for controlling provides for concurrent execution of said instructions, said controlling means controlling the initiation of said concurrent execution of instructions based on the availability of said functional unit means for the processing of data.
Claim 6
Dependent Claim
23 words
The computer system according to claim 3, further comprising: means, coupled between said obtaining means and said execution means, for buffering said instructions.
Claim 7
Dependent Claim
23 words
The computer system according to claim 4, further comprising: means, coupled to said buffering means, for simultaneously performing decoding of said buffered instructions.
Claim 8
Dependent Claim
29 words
The computer system according to claim 4, further comprising: means, coupled to said buffering means, for simultaneously performing renaming of source and destination register operands for said buffered instructions.
Claim 9
Dependent Claim
49 words
The computer system according to claim 3, further comprising: means for determining whether all instructions in said predetermined program order have been executed and means, responsive to said determining means and coupled to said storing means, for transferring the data stored by said temporary register to said predetermined register.
Claim 10
Dependent Claim
156 words
A superscalar microprocessor, comprising: a fetch unit to retrieve instructions from a memory in a predetermined program order, wherein one of said instructions includes a register reference; a register file including a predetermined register and a temporary register, wherein said temporary register stores out-of-order execution results; an execution unit, operably coupled with said fetch unit, including a plurality of functional units, wherein said plurality of functional units concurrently execute at least two of said instructions based on availability of at least two of said plurality of functional units, and execute said one of said instructions out of said predetermined program order and store an execution result in said temporary register based on said register reference, rather than in said predetermined register; a retirement unit to retire said instructions in said predetermined program order; and data bus system to route data between one of said predetermined register and said temporary register, and said plurality of functional units.
Claim 11
Dependent Claim
156 words
A superscalar microprocessor, comprising: a fetch unit to retrieve instructions from a memory in a predetermined program order, wherein one of said instructions includes a register reference; a register file including a predetermined register and a temporary register, wherein said temporary register stores out-of-order execution results; an execution unit, operably coupled with said fetch unit, including a plurality of functional units, wherein said plurality of functional units concurrently execute at least two of said instructions based on availability of at least two of said plurality of functional units, and execute said one of said instructions out of said predetermined program order and store an execution result in said temporary register based on said register reference, rather than in said predetermined register; a retirement unit to retire said instructions in said predetermined program order; and data bus system to route data between one of said predetermined register and said temporary register, and said plurality of functional units.
Claim 12
Dependent Claim
25 words
The superscalar microprocessor according to claim 8, further comprising: an instruction buffer, coupled between said fetch unit and said execution unit, for buffering said instructions.
Claim 13
Dependent Claim
19 words
The superscalar microprocessor according to claim 9, further comprising: means, coupled to said fetch unit, for performing branch prediction.
Claim 14
Dependent Claim
23 words
The superscalar microprocessor according to claim 9, further comprising: means, coupled to said register file, for performing register renaming and data dependency checking.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-11-17 | 2001-05-19 | 2001-11-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-11-17 | 2005-05-19 | 2005-11-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-11-17 | 2009-05-19 | 2009-11-18 | $7700.00 | Window Closed / Lapsed |