Pipeline data processor

Claim 2

A data processor for executing in a pipeline system instructions controlled by a wired logic control, comprising: a program counter (101; 3201) for indicating an address of an instruction to be read; m (m = 2, 3, ...) instruction registers (104, 105; 3204-3207) for storing at a time in one machine cycle a sequence of m instructions of which the first address is indicated by said program counter; a register file (111; 3216) formed of a plurality of registers in which data are stored; and m arithmetic operation units (110, 112; 3214, 3215, 3217, 3218) which read corresponding data from said register file and carry out parallelly arithmetic operations in accordance with instructions read from said instruction registers; whereby the contents of said program counter is increased by m at a time, sequential m instructions are read from the addresses pointed by said program counter and written in said instruction registers, and said m instructions are processed in parallel by said m arithmetic operation units.

Claim 3

A data processor according to claim 1, wherein said instructions have a fixed length, and the number of instructions to be processed in one machine cycle satisfies m = 2 n (n = 1, 2, ...).

Claim 4

A data processor according to claim 1, further comprising: means (2300; 2604) for detecting whether one instruction of said m instructions has a conflict with a subsequent instruction or not; and means for controlling to substantially execute only said one instruction in one machine cycle when said detection means detected said conflict.

Claim 5

A data processor according to claim 3, wherein while only said one instruction is substantially being executed in one machine cycle, said control means controls the other instructions to be executed with NOP instruction.

Claim 6

A data processor according to claim 3, wherein said detection means detects said conflict by deciding whether or not said subsequent instruction reads the register in which data is written by said one instruction.

Claim 7

A data processor according to claim 3, wherein said detection means is constructed to access only once to a memory in one machine cycle and detects said conflict by deciding whether each of said one instruction and said subsequent instruction is a load instruction or a store instruction.

Claim 8

A data processor according to claim 3 wherein said detection means detects said conflict on the basis of the facts that some arithmetic operation units of said m arithmetic operation units have a barrel shifter (1501), that at least one of said one instruction and said subsequent instruction is a bit shift instruction, and that the arithmetic operation unit for processing said bit shift instruction has no barrel shifter.

Claim 9

A data processor according to claim 3, further comprising: a cache memory for instructions which is provided before said instruction registers; wherein said detection means includes means (2300) for writing a conflict bit indicating said conflict at every m instructions which are read at a time, within said cache memory.

Claim 10

A data processor according to claim 3, further comprising: a cache memory for instructions which is provided before said instruction registers; wherein said detection means includes means (2604) for monitoring at each machine cycle the conflict between instructions produced from said cache memory.

Claim 11

A data processor according to claim 1, wherein an instruction for altering a status flag and a branch instruction of which the branch condition is satisfied by said status flag is included in the m instructions read by said program counter and there is provided means for detecting presence of a conditional branch instruction at a predetermined address to suppress execution of instructions after a corresponding address of the m instructions when the condition is satisfied.

Claim 12

A data processor according to claim 1, wherein part of the memory in which instructions are stored is formed of a ROM.

Claim 13

A data processor according to claim 1, wherein any interrupt is inhibited between the m instructions which are read at a time.

Claim 14

A data processor for executing in a pipeline system an instruction controlled by wired logic control, comprising: a program counter (101; 3201) for indicating the address of instructions to be read; m (m = 2, 3, ...) instruction registers (104, 105; 3204-3207) for storing at a time in one machine cycle sequentially m instructions of which the first address is indicated by said program counter; a register file (111; 3216) formed of a plurality of registers in which data is stored; and m arithmetic operation units (110, 112; 3214, 3215, 3217, 3218) for reading corresponding data from said register file and making arithmetic operations in parallel in accordance with the instructions read from said instruction registers; whereby only when the contents of said program counter is within a limited range, sequential m instruc­tions of which the first address is indicated by said program counter are read and written in said instruction registers, said m instructions are processed by said m arithmetic operation units, and when the contents of said program counter is out of said range, ℓ (ℓ > m, ℓ = 1, 2, ...) instructions are read in said instruction registers and processed in parallel by ℓ arithmetic operation units.

Claim 15

A data processor for executing in a pipeline system an instruction controlled by wired logic control, comprising: a program counter (101; 3201) for indicating the address of instructions to be read; m (m = 2, 3, ...) instruction registers (104, 105; 3204-3207) for storing at a time in one machine cycle sequentially m instructions of which the first address is indicated by said program counter; a register file (111; 3216) formed of a plurality of registers in which data is stored; and m arithmetic operation units (110, 112; 3214, 3215, 3217, 3218) for reading corresponding data from said register file and making arithmetic operations in parallel in accordance with the instructions read from said instruction registers; whereby only when the contents of said program counter is within a limited range, sequential m instruc­tions of which the first address is indicated by said program counter are read and written in said instruction registers, said m instructions are processed by said m arithmetic operation units, and when the contents of said program counter is out of said range, ℓ (ℓ > m, ℓ = 1, 2, ...) instructions are read in said instruction registers and processed in parallel by ℓ arithmetic operation units.

Claim 16

A data processor according to claim 13, wherein said ℓ satisfies ℓ = 1.

Claim 17

A data processor according to claim 13, wherein said data processor is completely integrated on a one-chip semiconductor substrate, and at least part of a program within said range is integrated in form of a ROM on said semiconductor substrate.