Floating point arithmetic unit

Claim 2

A floating point arithmetic unit, characterized by the conbination of: an adder (2) having first and second inputs and an output; a multiplier (4) having first and second inputs and an output; a first bus (12) connected to said adder's first and second inputs and output, and also connected to said multiplier's first and second inputs; a second bus (13) connected to said multiplier's first and second inputs and output, and also connected to said adder's first and second inputs; and a register file (8) having at least a first input connected to said first bus and a second input connected to said second bus and at least first and second outputs (22, 24) connected to inputs of said adder and multiplier, with each register stage in the register file including a source register for keeping track of the source of any result on each bus so the respective register stages may be connected to the correct one of said first and second busses on which a result is to appear.

Claim 3

Arithmetic unit, according to claim 1, characterized by: an adder unit (7) having a left adder wait station (14) and a right adder wait station (16), and including an adder output; a multiplier unit (4) having a left multiplier wait station (18) and a right multiplier wait station (20), and including a multiplier output; an adder putaway bus (6) connected to said adder output; a multiplier putaway bus (10) connected to said multiplier output: an adder bypass bus (12) connected to said adder putaway bus and connected to each of said left and right adder wait stations and said left and right multiplier wait stations; a multiplier bypass bus (13) connected to said multiplier putaway bus and connected to each of said left and right adder wait stations and said left and right multiplier wait stations; and a register file (8) having n registers (R1-Rn), where n is an integer, with each of the registers having a value field (Fig. 2) indicative of the operand value, a busy bit having two states, when in the first state indicating that the value field is invalid and when in a second state indicating that the value field is valid, and a source bit having two states indicative of which putaway bus to monitor when waiting for the result of a floating point arithmetic operation which is to be stored in said value field, with said adder putaway bus being monitored when said source bit is in the first state indicative of an adder type operation. and with said multiplier putaway bus being monitored when said source bit is in the second state indicative of a multiplier type operation.

Claim 4

Arithmetic unit according to claims 1 and 2, wherein said adder wait station and said multiplier wait station each include m registers (Fig. 3), where m is an integer, with each of said m registers including at least a valid bit, two ready bits and two bus monitor bits, with said valid bit having two states, when m the first state being indicative of an instruction being placed in the register, and when in the second state indicating that an operand has not been placed in the register, with said ready bits having two states, when in the first state being indicative of the respective operand being ready for an arithmetic operation, and when in the second state being indicative of the operand not being ready for an arithmetic operation, with said bus monitor bits having two states indicative of which bypass bus to monitor when waiting for the result of a floating point arithmetic operation, when in the first state being indicative that the adder putaway bus should be monitored for a floating point add type result, and when in the second state being indicative that the multiplier putaway bus should be monitored for a floating point multiply type result.