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EP0354585A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Instruction pipeline microprocessor

Assignee: Toshiba Corp
•
Filing: 1989-08-11
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Granted: —
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Expires: 2009-08-11
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Abstract

Abstract An instruction pipeline type microprocessor comprises an operation execution section consisting of a first operation execution section (10) for executing instructions having no memory operand, a second operation execution section (11) for executing instructions having memory operand respectively, and a third operation execution section (12) for executing floating point instructions, and a general purpose register (8 min ) consisting of a second register group for storing data processed as a result executed by the operation execution section (10) in the form of flow of programs and a first register group for storing processed data as the result of a lock-forward execution of instructions which can be processed by the operation execution section(10) and compare and decision means for determining whether or not succeeding instructions have been executed by jumping preceding instructions is made and for sending processed data held in the first register group to the second register group so as to be exchanged along a program flow in accordance with the result of the determination.

Inventors

  • 👤 Kosei Okamoto

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 02:54
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3867; G06F9/3873; G06F9/3836; G06F9/3885

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 162 words
An instruction pipeline type microprocessor, comprising: (a) a plurality of operation execution sections for executing a plurality of decoded different kinds of instructions simultaneously in accordance with the different kinds of instructions; (b) a first storing means for storing processed data as a result of having in look-forward manner executed instructions capable of processing by said plurality of operation execution sections; (c) a second storing means for storing the processed data as a result of one executed by said operation execution sections in the form along a predetermined program flow; and (d) a compare and decision means for determining whether or not succeeding instructions are executed by jumping preceding instructions among instructions successively issued and decoded along the predetermined program flow and for sending the processed data stored in said first storing means to said second storing means so as to be replaced in the form along the predetermined program flow, whereby processable succeeding instructions can be executed in a look-forward manner.
Claim 2
Dependent Claim 162 words
An instruction pipeline type microprocessor, comprising: (a) a plurality of operation execution sections for executing a plurality of decoded different kinds of instructions simultaneously in accordance with the different kinds of instructions; (b) a first storing means for storing processed data as a result of having in look-forward manner executed instructions capable of processing by said plurality of operation execution sections; (c) a second storing means for storing the processed data as a result of one executed by said operation execution sections in the form along a predetermined program flow; and (d) a compare and decision means for determining whether or not succeeding instructions are executed by jumping preceding instructions among instructions successively issued and decoded along the predetermined program flow and for sending the processed data stored in said first storing means to said second storing means so as to be replaced in the form along the predetermined program flow, whereby processable succeeding instructions can be executed in a look-forward manner.
Claim 3
Dependent Claim 51 words
The microprocessor as claimed in claim 1, wherein said plurality of operation execution sections include a first operation execution section for executing instructions having no memory operand respectively, a second operation execution section for executing instructions having a memory operand respectively, and a third operation execution for executing floating point instructions.
Claim 4
Dependent Claim 147 words
The microporcessor as claimed in claim 1, wherein each of said plurality of operation execution sections has an instruction register having at least an instruction address holding field indicative of an address of an instruction decoded on a program and a destination register designation field for designating each of memory locations for the processed data, and said compare and decision means comprising a comparator for comparing each address from the address holding field of said each instruction register and for producing the result of the comparisons, and a plurality tag bits provided at said first storing means, so as to be selected by the resulting signals from the comparator and the designation of said destination register designation field, whereby the processed data in the first storing means is sent to the second storing means so as to be replaced in the form along the predetermined program flow.
Claim 5
Dependent Claim 50 words
The microprocessor as claimed in claim 2, wherein said first storing means is comprised of register group for successively storing the result of the operations about instructions executed, and said second storing means in comprised of register group for storing the results of the operations along the predetermined program flow.

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