§
Luxuse
Patent Intelligence
Sign In
← Back to Patent Explorer
EP0377991A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Data processing systems

Assignee: International Business Machines Corp
•
Filing: 1989-12-20
•
Granted: —
•
Expires: 2009-12-20
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

Inventors

  • 👤 Gregory Frederick Grohoski
  • 👤 James Allan Kahle
  • 👤 Myhong Nguyenphu
  • 👤 David Scott Ray

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 11:37
CPC Classifications
G; G06; G06F; G06F7/00; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/30; G06F9/38; G06F9/3818; G06F9/3822; G06F9/3836; G06F9/3861; G06F9/3877; G06F9/3885

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 80 words
A data processing system comprising: an instruction storage means for storing a sequence of instructions requiring operation by at least two processor means; a plurality of processor means for executing instructions from the instruction storage means; instruction dispatch means for dispatching each instruction to at least one of the processor means; and at least one of the processor means including means for executing dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor means.
Claim 2
Dependent Claim 80 words
A data processing system comprising: an instruction storage means for storing a sequence of instructions requiring operation by at least two processor means; a plurality of processor means for executing instructions from the instruction storage means; instruction dispatch means for dispatching each instruction to at least one of the processor means; and at least one of the processor means including means for executing dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor means.
Claim 3
Dependent Claim 42 words
A system as claimed in Claim 1, wherein the means for executing dispatched instructions before the execution of the preceding instruction further includes means for delaying execution of an instruction ahead of sequence when the instruction requires operations by another processor means.
Claim 4
Dependent Claim 65 words
A system as claimed in Claim 1 or Claim 2, wherein the means for executing dispatched instructions before the execution of the preceding instruction further includes means for delaying execution of an interruptable instruction of a type capable of generating an interrupt condition for the processor means until the interruptable instruction is executed in sequential order with the execution of other instructions in the sequence.
Claim 5
Independent Claim 43 words
A system as claimed in any preceding Claim, wherein the instruction dispatch means includes means for detecting the occurrence of an interrupt and in response thereto, for dispatching instructions of the sequence in the order previously dispatched before the occurrence of the interrupt.
Claim 6
Independent Claim 43 words
A system as claimed in any preceding Claim, wherein the means for executing dispatched instructions before the execution of the preceding instruction further includes means for delaying execution of an instruction ahead of sequence when the instruction requires operation by another processor means.
Claim 7
Independent Claim 40 words
A system as claimed in any preceding Claim, wherein the instruction storage means includes the sequence of instruction for the at least two processor means and the instruction dispatch means dispatches each instruction to the at least two processor means.
Claim 8
Dependent Claim 23 words
A system as claimed in Claim 6, wherein the instruction sequence includes at least one instruction that requires the operations of two processors.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag