Instruction control mechanism for a computing system with register renaming, map table and queues indicating available registers

Claim 2

A register renaming apparatus for a computing system having a main memory comprising addressable locations containing data and instructions, said instructions including a plurality of fields including an operation field specifying an operation to be performed and at least one register designation field, each such register designation field being indicative to two of n architectures registers for receiving data according to the operation specified in said operation field, said computing system including m physical registers, where m>n, comprising: a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers, with the architected register designation in said register designation field being replaced by the physical register number in the corresponding location in said map table prior to the associated instruction being executed; a free list of the ones of said m physical registers which are currently not assigned to architected register locations in said map table, and which are available for future assignment to said map table; a holding register queue which receives remapped physical register designations from said map table of certain ones of said physical registers which are being utilized by instructions presently being executed, with said holding register queue temporarily storing said certain one of said physical register designations prior to entering them in said free list of physical registers following the execution of their associated instructions; and a store queue which has a physical register designation stored therein of a store operation to a register designated in said map table; means for comparing physical register designations stored in the store queue with the physical register designations stored in said holding register queue, which have executed their associated instructions, with all such physical register designations in the holding register queue which do not compare being made available to the free list; and means for determining that all stores are complete for the physical register designations that do compare, with such physical register designations that compare being made available to the free list following the determination that all associated stores are complete.

Claim 3

A register renaming apparatus for two instructions at a time for a coprocessor system having a main memory comprising addressable locations containing data and instructions, said instructions including a plurality of fields including an operation field specifying an operation to be performed and at least two register designation fields, each such register designation field including a tag indicative of one of n architected registers for receiving data according to the operation specified in said operation field, said computing system including a physical registers, where m>n, comprising: a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers, with the architected register tag in said register designation field being replaced by a physical register number tag in the corresponding location in said map table prior to the associated instruction being executed; a free list of the tags of the ones of said m physical registers which are currently not associated to architected register locations in said map table, and which are available for future assignment to said map table; a pending target return queue which receives remapped physical register tags from said map table of certain ones of said physical registers which are being utilized by instructions presently being executed, with said pending target return queue temporarily storing said certain ones of said physical register tags prior to entering them in said free list of physical registers following the execution of their associated instructions; and a store queue which has a physical register tag stored therein of a floating point store operation to a register designated in said map table, said store queue including means for comparing the physical register tags stored therein with the physical register tags stored in said pending target return queue which have executed their associated instructions, with all such physical tags in the pending target return queue which do not compare being made available to said free list, said store queue including means for determining that all stores are complete for the physical register tags that do compare, with such physical register tags that compare being made available to the free list following the determination that all associated stores are completed.

Claim 4

A register renaming apparatus for two instructions at a time for a coprocessor system having a main memory comprising addressable locations containing data and instructions, said instructions including a plurality of fields including an operation field specifying an operation to be performed and at least two register designation fields, each such register designation field including a tag indicative of one of n architected registers for receiving data according to the operation specified in said operation field, said computing system including a physical registers, where m>n, comprising: a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers, with the architected register tag in said register designation field being replaced by a physical register number tag in the corresponding location in said map table prior to the associated instruction being executed; a free list of the tags of the ones of said m physical registers which are currently not associated to architected register locations in said map table, and which are available for future assignment to said map table; a pending target return queue which receives remapped physical register tags from said map table of certain ones of said physical registers which are being utilized by instructions presently being executed, with said pending target return queue temporarily storing said certain ones of said physical register tags prior to entering them in said free list of physical registers following the execution of their associated instructions; and a store queue which has a physical register tag stored therein of a floating point store operation to a register designated in said map table, said store queue including means for comparing the physical register tags stored therein with the physical register tags stored in said pending target return queue which have executed their associated instructions, with all such physical tags in the pending target return queue which do not compare being made available to said free list, said store queue including means for determining that all stores are complete for the physical register tags that do compare, with such physical register tags that compare being made available to the free list following the determination that all associated stores are completed.

Claim 5

In a central processor-coprocessor system, the combination comprising: a main memory comprising addressable locations containing data and instructions, said instructions including a plurality of fields including an operation code field specifying an operation to be performed such as a load operation or a store operation or a floating point arithmetic operation, and at least two register designation fields, each such register designation field including a register tag indicative of one of n, where n is an integer, architected registers for receiving data according to said operational code field; a central processor which provides address information to the addressable address locations of said main memory for receiving instructions and data, and also providing a synchronization signal for a coprocessor; a coprocessor comprising: a control unit for receiving said synchronization signal from said central processor unit and instructions from said main memory; a register field comprised of m, where m is an integer, physical registers for receiving data from main memory according to said instructions, and addresses from said control unit; a floating point arithmetic unit for receiving unit data from said register file and said main memory in accordance with said instructions and receiving control information from said control unit; register renaming means for receiving the architected register tags of instructions from said control unit, and providing physical register tags in place of said architected register tags to said control unit, said register renaming means comprising: a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers in said register file, with the architected register tag in said register designation field being replaced by the physical register number tag in the corresponding location in said map table prior to the associated instruction being executed; a free list of the tags of the ones of said physical registers in said register file which are currently not assigned to architected register locations in said map table, and which are available for future assignment to said map table; a pending target return queue which receives physical register tags from said map table of certain ones of said physical registers in said register file which are being utilized by said floating point arithmetic unit, with said pending target return queue temporarily storing said physical register tags prior to entering them in said free list of physical registers following the execution of their associated instruction; and a store queue which has a physical register tag stored therein of a store to a register designated in said map table, said store queue including means for comparing the physical register tags stored therein with the physical register tags stored in said pending target return queue which have executed their associated instructions with all such physical tags in said pending target return queue which do not compare being made available to the free list, said store queue including means for determining that all stores are complete for the physical register tags that do compare, with such physical register tags that do compare being made available to the free list following the determination that all associated stores are complete.

Claim 6

In a central processor-coprocessor system, the combination comprising: a main memory comprising addressable locations containing data and instructions, said instructions including a plurality of fields including an operation code field specifying an operation to be performed such as a load operation or a store operation or a floating point arithmetic operation, and at least two register designation fields, each such register designation field including a register tag indicative of one of n, where n is an integer, architected registers for receiving data according to said operational code field; a central processor which provides address information to the addressable address locations of said main memory for receiving instructions and data, and also providing a synchronization signal for a coprocessor; a coprocessor comprising: a control unit for receiving said synchronization signal from said central processor unit and instructions from said main memory; a register field comprised of m, where m is an integer, physical registers for receiving data from main memory according to said instructions, and addresses from said control unit; a floating point arithmetic unit for receiving unit data from said register file and said main memory in accordance with said instructions and receiving control information from said control unit; register renaming means for receiving the architected register tags of instructions from said control unit, and providing physical register tags in place of said architected register tags to said control unit, said register renaming means comprising: a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers in said register file, with the architected register tag in said register designation field being replaced by the physical register number tag in the corresponding location in said map table prior to the associated instruction being executed; a free list of the tags of the ones of said physical registers in said register file which are currently not assigned to architected register locations in said map table, and which are available for future assignment to said map table; a pending target return queue which receives physical register tags from said map table of certain ones of said physical registers in said register file which are being utilized by said floating point arithmetic unit, with said pending target return queue temporarily storing said physical register tags prior to entering them in said free list of physical registers following the execution of their associated instruction; and a store queue which has a physical register tag stored therein of a store to a register designated in said map table, said store queue including means for comparing the physical register tags stored therein with the physical register tags stored in said pending target return queue which have executed their associated instructions with all such physical tags in said pending target return queue which do not compare being made available to the free list, said store queue including means for determining that all stores are complete for the physical register tags that do compare, with such physical register tags that do compare being made available to the free list following the determination that all associated stores are complete.

Claim 7

In a central processor-coprocessor system, the combination comprising: a main memory comprising addressable locations containing data and instructions, said instructions including a plurality of fields including an operation code field specifying an operation to be performed such as a load operation or a store operation or a floating point arithmetic operation, and at least two register designation fields, each such register designation field including a register tag indicative of one of n, where n is an integer, architected registers for receiving data according to said operational code field; a central processor which processes said load and store operations, and provides address information to the addressable address locations of said main memory for receiving instructions and data, and also providing a synchronization signal for a coprocessor; a coprocessor which processes said floating point arithmetic operations, comprising: a control unit for receiving said synchronization signal from said central processor unit and instructions from said main memory, said control unit comprising: a synchronization unit which receives said synchronization signal from said central processor unit, and separates the operation code field from the architected register tags in each instruction; an instruction decode buffer which receives the operation code field from said synchronization unit and physical register tags from a register remaining means for each instruction; and a decoder for receiving instructions from said instruction decode buffer and decoding them for provision to a register file and arithmetic unit; a register file comprised of m, where m is an integer, physical registers for receiving data from main memory according to said instructions, and addresses from said decoder; a floating point arithmetic unit for receiving data from said register file and said main memory in accordance with said instructions and receiving control information from said decoder; register remaining means for receiving the architected register tags of instructions from said synchronization unit, and providing physical register tags in place of said architected register tags to said instruction decode buffer, said register renaming means comprising: a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers in said register file, with the architected register tag in said register designation field being replaced by the physical register number tag in the corresponding location in said map table prior to the associated instruction being executed; a free list of the tags of the ones of said physical registers in said register file which are currently not assigned to architected register locations in said map table, and which are available for future assignment to said map table; a pending target return queue which receives physical register tags from said map table of certain ones of said physical registers in said register file which are being utilized by said floating point arithmetic unit, with said pending target return queue temporarily storing said physical register tags prior to entering them in said free list of physical registers following the execution of their associated instructions; and a store queue which has a physical register tag stored therein of a store to a register designated in said map table, said store queue including means for comparing the physical register tag stored therein with the physical register tags stored in said pending target return queue which have executed their associated instructions, with all such physical tags in said pending target return queue which do not compare being made available to the free list, said store queue including means for determining that all stores are complete for the physical register tags that do compare, with such physical register tags that do compare being made available to the free list following the determination that all associated stores are complete.

Claim 8

In a central processor-coprocessor system, the combination comprising: a main memory comprising addressable locations containing data and instructions, said instructions including a plurality of fields including an operation code field specifying an operation to be performed such as a load operation or a store operation or a floating point arithmetic operation, and at least two register designation fields, each such register designation field including a register tag indicative of one of n, where n is an integer, architected registers for receiving data according to said operational code field; a central processor which processes said load and store operations, and provides address information to the addressable address locations of said main memory for receiving instructions and data, and also providing a synchronization signal for a coprocessor; a coprocessor which processes said floating point arithmetic operations, comprising: a control unit for receiving said synchronization signal from said central processor unit and instructions from said main memory, said control unit comprising: a synchronization unit which receives said synchronization signal from said central processor unit, and separates the operation code field from the architected register tags in each instruction; an instruction decode buffer which receives the operation code field from said synchronization unit and physical register tags from a register remaining means for each instruction; and a decoder for receiving instructions from said instruction decode buffer and decoding them for provision to a register file and arithmetic unit; a register file comprised of m, where m is an integer, physical registers for receiving data from main memory according to said instructions, and addresses from said decoder; a floating point arithmetic unit for receiving data from said register file and said main memory in accordance with said instructions and receiving control information from said decoder; register remaining means for receiving the architected register tags of instructions from said synchronization unit, and providing physical register tags in place of said architected register tags to said instruction decode buffer, said register renaming means comprising: a map table having n locations indicative of said n architected registers, with each entry in said n locations containing the number of different ones of said m physical registers in said register file, with the architected register tag in said register designation field being replaced by the physical register number tag in the corresponding location in said map table prior to the associated instruction being executed; a free list of the tags of the ones of said physical registers in said register file which are currently not assigned to architected register locations in said map table, and which are available for future assignment to said map table; a pending target return queue which receives physical register tags from said map table of certain ones of said physical registers in said register file which are being utilized by said floating point arithmetic unit, with said pending target return queue temporarily storing said physical register tags prior to entering them in said free list of physical registers following the execution of their associated instructions; and a store queue which has a physical register tag stored therein of a store to a register designated in said map table, said store queue including means for comparing the physical register tag stored therein with the physical register tags stored in said pending target return queue which have executed their associated instructions, with all such physical tags in said pending target return queue which do not compare being made available to the free list, said store queue including means for determining that all stores are complete for the physical register tags that do compare, with such physical register tags that do compare being made available to the free list following the determination that all associated stores are complete.