EP0419105A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Integrated circuit having an embedded digital signal processor
Assignee: Texas Instruments Inc
•
Filing: 1990-09-10
•
Granted: —
•
Expires: 2010-09-10
Abstract
Abstract An integrated circuit chip comprises a digital signal processor core (12) formed on a portion of the surface area of the chip (10). The digital signal processor (12) has a read only memory (14), a random access memory (16), a register file (18), an arithmetic logic unit (20) and a multiplier circuit (22). The remaining surface area of the integrated circuit chip (10) forms a user-definable circuitry area (24) which is used to form added circuitry to interface the digital signal processor (12) with other components of an integrated data processing system. The circuits formed in the user-definable circuitry area (24) are coupled to other integrated circuit chips through universal input/output bond pads (28). In one embodiment of the present invention, parallel module testing multiplexers (26) are added to aid in the testing of the digital signal processor (11) and the added circuits formed in the user-definable circuitry area (24).
Inventors
- 👤 Uming U-Ming Ko
- 👤 Bernhard H. Andresen
- 👤 Glen R. Balko
- 👤 Stanley C. Keeney
- 👤 Joe F. Sexton
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 10:34
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318522; G06F15/7867
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
71 words
An integrated circuit formed on a surface of a semiconductor substrate, comprising: a digital signal processor circuit formed on a portion of the surface of the substrate; and a plurality of added circuits formed on a portion of the remainder of the surface of the substrate coupled to said digital signal processor circuit operating in conjunction with said digital signal processor circuit and external electronic components coupled to the integrated circuit.
Claim 2
Dependent Claim
71 words
An integrated circuit formed on a surface of a semiconductor substrate, comprising: a digital signal processor circuit formed on a portion of the surface of the substrate; and a plurality of added circuits formed on a portion of the remainder of the surface of the substrate coupled to said digital signal processor circuit operating in conjunction with said digital signal processor circuit and external electronic components coupled to the integrated circuit.
Claim 3
Dependent Claim
91 words
The circuit of Claim 1, and further comprising: a signal path coupling said digital signal processor to at least one of said plurality of added circuits, said signal path solely coupling circuitry resident on the substrate; a testing signal path for testing said digital signal processor; and multiplexing circuitry coupled to said signal path and responsive to a test signal such that said signal path is selectively accessible through said testing signal path, said testing signal bath coupled to said multiplexing circuitry such that said digital signal processor may be tested.
Claim 4
Dependent Claim
66 words
The circuit of Claim 1, wherein said digital signal processor circuit comprises: memory circuitry for storing programs and operands used by said digital signal processor; an arithmetic logic unit coupled to said memory circuitry and operable to perform arithmetic operations on said operands; and a multiplier circuit coupled to said memory circuitry and said arithmetic logic unit and operable to perform multiplication operations on said operands.
Claim 5
Dependent Claim
90 words
The circuit of Claim 1, and further comprising: a signal path coupling at least two of said added circuits, said signal path solely coupling circuitry resident on the substrate and not directly interfacing with the external components; a testing signal path for testing said added circuits; and multiplexing circuit coupled to said signal path and responsive to a test signal such that said signal path is selectively accessible through said testing signal path, said testing signal path coupled to said multiplexing circuitry such that said added circuits may be tested.
Claim 6
Dependent Claim
19 words
The circuit of Claim 1, wherein the integrated circuit occupies less than 100 square millimeters of semiconductor surface area.
Claim 7
Dependent Claim
70 words
An integrated circuit formed on a surface of a semiconductor substrate, comprising: a digital signal processor circuit formed on a portion of the surface of the substrate; and a gate array formed on a portion of the remainder of the surface of the substrate, said gate array programmable by further processing to operate in conjunction with said digital signal processor circuit and external electronic components coupled to the integrated circuit.
Claim 8
Dependent Claim
70 words
An integrated circuit formed on a surface of a semiconductor substrate, comprising: a digital signal processor circuit formed on a portion of the surface of the substrate; and a gate array formed on a portion of the remainder of the surface of the substrate, said gate array programmable by further processing to operate in conjunction with said digital signal processor circuit and external electronic components coupled to the integrated circuit.
Claim 9
Dependent Claim
74 words
The circuit of Claim 6, and further comprising: a signal path coupling said digital signal processor circuit to said gate array, said signal path solely coupling circuitry resident on the substrate; a testing signal path for testing said digital signal processor; and multiplexing circuitry for coupling to a selected one of said signal path and said testing signal path, said multiplexing circuitry coupling to said testing signal path responsive to receiving a test signal.
Claim 10
Dependent Claim
66 words
The circuit of Claim 6, wherein said digital signal processor circuit comprises: memory circuitry for storing programs and operands used by said digital signal processor; an arithmetic logic unit coupled to said memory circuitry and operable to perform arithmetic operations on said operands; and a multiplier circuit coupled to said memory circuitry and said arithmetic logic unit and operable to perform multiplication operations on said operands.
Claim 11
Dependent Claim
20 words
The circuit of Claim 6, wherein the integrated circuit occupies less than 100 square millimeters of semiconductor substrate surface area.
Claim 12
Dependent Claim
237 words
An integrated circuit formed on a surface of a semiconductor substrate, comprising: a digital signal processor circuit formed on the surface of the substrate, said digital signal processor circuit comprising memory circuitry for storing programs and operands used by said digital signal processor circuit, an arithmetic logic unit coupled to memory circuitry for performing arithmetic operations on said operands and a multiplier circuit coupled to said memory circuitry and said arithmetic logic unit for performing multiplication operations on said operands; a plurality of bond pads formed on the surface of the substrate; a gate array formed on the surface of the substrate, said gate array programmable to be coupled to said digital signal processor circuit and said bond pads and to form circuitry to operate in conjunction with said digital signal processor circuit and external components coupled to said integrated circuit through said bond pads; at least one signal path coupling said digital processor circuit to said gate array, said signal path not directly coupled to any of said bond pads; a testing signal path for testing said digital processor circuit; and multiplexing circuitry coupled to said signal path and responsive to a test signal such that said signal path is selectively accessible through said testing signal path, said testing signal path coupling said multiplexing circuitry to at least one of said bond pads such that said digital signal processor may be tested through said bond pads.
Claim 13
Dependent Claim
237 words
An integrated circuit formed on a surface of a semiconductor substrate, comprising: a digital signal processor circuit formed on the surface of the substrate, said digital signal processor circuit comprising memory circuitry for storing programs and operands used by said digital signal processor circuit, an arithmetic logic unit coupled to memory circuitry for performing arithmetic operations on said operands and a multiplier circuit coupled to said memory circuitry and said arithmetic logic unit for performing multiplication operations on said operands; a plurality of bond pads formed on the surface of the substrate; a gate array formed on the surface of the substrate, said gate array programmable to be coupled to said digital signal processor circuit and said bond pads and to form circuitry to operate in conjunction with said digital signal processor circuit and external components coupled to said integrated circuit through said bond pads; at least one signal path coupling said digital processor circuit to said gate array, said signal path not directly coupled to any of said bond pads; a testing signal path for testing said digital processor circuit; and multiplexing circuitry coupled to said signal path and responsive to a test signal such that said signal path is selectively accessible through said testing signal path, said testing signal path coupling said multiplexing circuitry to at least one of said bond pads such that said digital signal processor may be tested through said bond pads.
Claim 14
Dependent Claim
20 words
The circuit of Claim 10, wherein the integrated circuit occupies less than 100 square millimeters of semiconductor substrate surface area.
Claim 15
Dependent Claim
25 words
The circuit of Claim 10, wherein the digial signal processor circuit occupies no more than 55 percent of the surface area of the substrate surface.
Claim 16
Dependent Claim
22 words
The circuit of Claim 10, wherein the gate array occupies at least 45 percent of the surface area of the substrate surface.
Claim 17
Independent Claim
56 words
A method for constructing an integrated circuit on a surface of a semiconductor substrate, comprising the steps of: forming a digital signal processor on a portion of the surface of the substrate; forming a plurality of transistors in a gate array on another portion of the surface of the substrate that are programmable by further processing.
Claim 18
Independent Claim
56 words
A method for constructing an integrated circuit on a surface of a semiconductor substrate, comprising the steps of: forming a digital signal processor on a portion of the surface of the substrate; forming a plurality of transistors in a gate array on another portion of the surface of the substrate that are programmable by further processing.
Claim 19
Dependent Claim
47 words
The method of Claim 14, and further comprising the steps of: forming interconnects between selected ones of the plurality of transistors and the digital signal processor to form circuitry operating in conjunction with the digital signal processor circuit and external electronic components coupled to the integrated circuit.
Claim 20
Dependent Claim
20 words
The method of Claim 12, wherein said integrated circuit occupies less than 100 square millimeters of semiconductor substrate surface area.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.