US5226170A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interface between processor and special instruction processor in digital data processing system
Assignee: Hewlett Packard Development Co LP
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Filing: 1991-07-17
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Granted: 1993-07-06
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Expires: 2011-07-17
Abstract
Abstract A processor and auxiliary processor for use in a digital data processing system, the auxiliary processor processing selected instructions, such as floating point instructions. The processor and auxiliary processor are interconnected by status lines, data lines and a bus to which other units in the system may also be connected. When the processor begins processing a selected instruction, it passes the instruction's operation code to the auxiliary processor over the data lines and enables the operands to be transferred to the auxiliary processor over the bus, along with information concerning each operand, which is transferred over the data lines. The processor then signals over the status lines that it is ready to receive the results. The auxiliary processor, when it has finished executing the special instruction, transmits a code over the status lines indicating it is sending the results, and transmits the condition codes over the data lines and the result data over the bus.
Inventors
- 👤 Paul I. Rubinfeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:51
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
308 words
A digital data processing system comprising: A. an information store for storing operands and instructions, at least some of said instructions including an operation code and an operand specifier, B. a central processing unit, connected by a bus to the information store, for retrieving operands and instructions to be executed form said information store over said bus, a portion of said bus carrying said operands and being connected directly between said information store and said central processing unit so that said retrieved operands are received by said central processing unit without passing through another unit in said system, and C. an auxiliary processor unit for executing instructions of selected types, said auxiliary processor unit being directly connected to said portion of said bus so that said auxiliary processor receives operands retrieved over said bus in parallel with said central processing unit, the central processing unit comprising: i. an operation code transfer circuit for transmitting to the auxiliary processor unit, an operation code form a retrieved instruction of a selected type; and ii. an operand transfer arrangement for processing each operand specifier, comprising: a. an operand locator responsive to an operand specifier for identifying to said auxiliary processor unit a source of an operand identified by said operand specifier, b. an operand transfer initiating circuit for initiating the transfer of an operand to the auxiliary processor unit by causing said operand to be placed on said portion of said bus, whereby said central processing unit maintains control of the transfer of said operand form said information store to said auxiliary processor over said portion of said bus; and the auxiliary processor unit including an operand receiver responsive to said operand source information from said operand locator and the initiating of an operand transfer by said operand transfer initiating circuit for receiving said operand from said portion of said bus.
Claim 2
Dependent Claim
308 words
A digital data processing system comprising: A. an information store for storing operands and instructions, at least some of said instructions including an operation code and an operand specifier, B. a central processing unit, connected by a bus to the information store, for retrieving operands and instructions to be executed form said information store over said bus, a portion of said bus carrying said operands and being connected directly between said information store and said central processing unit so that said retrieved operands are received by said central processing unit without passing through another unit in said system, and C. an auxiliary processor unit for executing instructions of selected types, said auxiliary processor unit being directly connected to said portion of said bus so that said auxiliary processor receives operands retrieved over said bus in parallel with said central processing unit, the central processing unit comprising: i. an operation code transfer circuit for transmitting to the auxiliary processor unit, an operation code form a retrieved instruction of a selected type; and ii. an operand transfer arrangement for processing each operand specifier, comprising: a. an operand locator responsive to an operand specifier for identifying to said auxiliary processor unit a source of an operand identified by said operand specifier, b. an operand transfer initiating circuit for initiating the transfer of an operand to the auxiliary processor unit by causing said operand to be placed on said portion of said bus, whereby said central processing unit maintains control of the transfer of said operand form said information store to said auxiliary processor over said portion of said bus; and the auxiliary processor unit including an operand receiver responsive to said operand source information from said operand locator and the initiating of an operand transfer by said operand transfer initiating circuit for receiving said operand from said portion of said bus.
Claim 3
Dependent Claim
31 words
The digital data processing system of claim 1 wherein the central processing unit further includes an operation code decoder for decoding the operation code to identify the selected type of instruction.
Claim 4
Dependent Claim
32 words
The digital data processing system of claim 2 wherein the auxiliary processor unit further includes an operation code decoder for decoding the received operation code to identify the number of associated operands.
Claim 5
Dependent Claim
36 words
The digital data processing system of claim 3 wherein instructions further include data type information, the central processing unit further including data type transfer circuit for transferring the data type information to the auxiliary processing unit.
Claim 6
Dependent Claim
59 words
The digital data processing system of claim 4 wherein the operand locator, in response to a selected operand specifier, identifies the information store as the source of a selected operand, and wherein the operand transfer initiating circuit includes an addressing circuit, connected to the information store, for providing an address to the information store to identify the selected operand.
Claim 7
Dependent Claim
83 words
The digital data processing system of claim 1 wherein said central processing unit and said auxiliary processing unit are connected by a set of status lines and by a set of data signal lines, and wherein said operation code transfer circuit of said central processing unit concurrently transmits said operation code to said auxiliary processor over said data signal lines and with said transmission, transmits operand type information over said status lines to identify to said auxiliary processor a type of said operand.
Claim 8
Dependent Claim
66 words
The digital data processing system of claim 6 wherein said auxiliary processor, after executing an instruction, concurrently transmits condition codes containing information concerning the result of said execution to said central processing unit over said data signal lines, and a ready code to said central processing unit over said status liens, the ready code indicating that it is ready to transmit the results of said execution.
Claim 9
Dependent Claim
279 words
A central processing unit for use in a digital data processing system, the digital data processing system including (i) an information store for storing operands and instructions, at least some of said instructions including an operation code and an operand specifier, (ii) a bus connecting the central processing unit to the information store, said central processing unit retrieving operands and instruction to be executed from said information store over said bus, a portion of said bus carrying said operands and being connected directly between said information store and said central processing unit so that said retrieved operands are received by said central processing unit without passing through another unit in said system, and (iii) an auxiliary processor unit for executing instructions of selected types, said auxiliary processor unit being directly connected to sad portion of said bus so that said auxiliary processor receives operands retrieved over said bus in parallel with said central processing unit, the central processing unit comprising: A. an operation code transfer circuit for transmitting to the auxiliary processor unit an operation code form a retrieved instruction of a selected type; B. an operand transfer arrangement for processing each operand specifier, comprising: i. an operand locator response to an operand specifier for identifying to is auxiliary processor unit a source of an operand identified by said operand specifier, ii. an operand transfer initiating circuit for initiating the transfer of an operand to the auxiliary processor unit by causing said operand to be placed on said potion of said bus, whereby said central processing unit maintains control of the transfer of said operand from said information store to said auxiliary processor over said portion of said bus.
Claim 10
Dependent Claim
279 words
A central processing unit for use in a digital data processing system, the digital data processing system including (i) an information store for storing operands and instructions, at least some of said instructions including an operation code and an operand specifier, (ii) a bus connecting the central processing unit to the information store, said central processing unit retrieving operands and instruction to be executed from said information store over said bus, a portion of said bus carrying said operands and being connected directly between said information store and said central processing unit so that said retrieved operands are received by said central processing unit without passing through another unit in said system, and (iii) an auxiliary processor unit for executing instructions of selected types, said auxiliary processor unit being directly connected to sad portion of said bus so that said auxiliary processor receives operands retrieved over said bus in parallel with said central processing unit, the central processing unit comprising: A. an operation code transfer circuit for transmitting to the auxiliary processor unit an operation code form a retrieved instruction of a selected type; B. an operand transfer arrangement for processing each operand specifier, comprising: i. an operand locator response to an operand specifier for identifying to is auxiliary processor unit a source of an operand identified by said operand specifier, ii. an operand transfer initiating circuit for initiating the transfer of an operand to the auxiliary processor unit by causing said operand to be placed on said potion of said bus, whereby said central processing unit maintains control of the transfer of said operand from said information store to said auxiliary processor over said portion of said bus.
Claim 11
Dependent Claim
25 words
The central processing unit of claim 8 further including an operation code decoder for decoding the operation code to identify the selected type of instruction.
Claim 12
Dependent Claim
35 words
The central processing unit of claim 9 wherein instructions further include data type information, the central processing unit further including data type transfer circuit for transferring the data type information to the auxiliary processing unit.
Claim 13
Dependent Claim
59 words
The central processing unit of claim 10 wherein the operand locator, in response to a selected operand specifier, identifies the information store as the source of a selected operand, and wherein the operand transfer initiating circuit includes an addressing circuit, for connection to the information store, for providing an address to the information store to identify the selected operand.
Claim 14
Dependent Claim
254 words
An auxiliary processor unit for executing instructions of selected types in a digital data processing system, the digital data processing system including (i) an information store for storing operands and instruction, at least some of said instructions including an operation code and an operand specifier, (ii) a central processing unit, connected by a bus to the information store, for retrieving operands and instructions to be executed from said information store over said bus, a portion of said bus carrying said operands and being connected directly between said information store and said central processing unit so that said retrieved operands are received by said central processing unit without passing through another unit in said system, the auxiliary processor unit being directly connected to said portion of said bus so that said auxiliary processor unit receives operands retrieved over said bus in parallel with said central processor unit, the auxiliary processor unit comprising: A. an operation code receiving circuit for receiving form the central processing unit an operation code form a retrieved instruction of a selected type; B. an operation code decoder or decoding the received operation code to identify the number of associated operands; and C. an operand receiver responsive to operand source information from the central processing unit, for receiving on said portion of said bus an operand from a source identified by the operand source information. wherein said central processing unit maintains control of the transfer of said operand form said information store to said auxiliary processor over said portion of said bus.
Claim 15
Dependent Claim
254 words
An auxiliary processor unit for executing instructions of selected types in a digital data processing system, the digital data processing system including (i) an information store for storing operands and instruction, at least some of said instructions including an operation code and an operand specifier, (ii) a central processing unit, connected by a bus to the information store, for retrieving operands and instructions to be executed from said information store over said bus, a portion of said bus carrying said operands and being connected directly between said information store and said central processing unit so that said retrieved operands are received by said central processing unit without passing through another unit in said system, the auxiliary processor unit being directly connected to said portion of said bus so that said auxiliary processor unit receives operands retrieved over said bus in parallel with said central processor unit, the auxiliary processor unit comprising: A. an operation code receiving circuit for receiving form the central processing unit an operation code form a retrieved instruction of a selected type; B. an operation code decoder or decoding the received operation code to identify the number of associated operands; and C. an operand receiver responsive to operand source information from the central processing unit, for receiving on said portion of said bus an operand from a source identified by the operand source information. wherein said central processing unit maintains control of the transfer of said operand form said information store to said auxiliary processor over said portion of said bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-05 | 1997-01-04 | 1997-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-05 | 2001-01-04 | 2001-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-05 | 2005-01-04 | 2005-07-06 | $7700.00 | Window Closed / Lapsed |