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EP0402856A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Instruction execution control system

Assignee: NEC Corp
•
Filing: 1990-06-12
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Granted: —
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Expires: 2010-06-12
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Abstract

Abstract The instruction execution control system of an information processing device having a pipeline instruction execution control portion is provided for sequentially executing an instruction interval between a completion of execution of a certain instruction and a read out of a next instruction. This system comprises program status word holding means (2) for holding program status word including indicating information concerning whether or not an instruction interval is to be sequentially executed and control information indicating execution status of program, and instruction execution sequencing indication means (4) responsive to the indicating information of the program status word held in the program status word holding means (2) for indicating the instruction execution control portion whether or not the instructions in the interval are to be sequentially executed. In this system an instruction in which program exception occurs can be easily identified, and a sequential execution of instruction interval between a completion of execution of a certain instruction and a readout of a next instruction only within a desired portion of a specific program can be easily performed.

Inventors

  • 👤 Kazuhisa Inoue

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 09:55
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30094; G06F9/30003; G06F9/30076; G06F9/38; G06F9/3861

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 111 words
An instruction execution control system for sequential executing an instruction interval in an information processing device having an instruction execution control portion utilizing a pipeline system, characterized by comprising program status word holding means for holding a program status word including an indicating information indicating whether or not the instruction interval is to be sequentially executed and a control information showing an execution status of a program and instruction execution sequencing indication means responsive to said indicating information of said program status word held in said program status word holding means to give said instruction execution control portion an indication whether or not said instruction interval is to be sequentially executed.
Claim 2
Dependent Claim 111 words
An instruction execution control system for sequential executing an instruction interval in an information processing device having an instruction execution control portion utilizing a pipeline system, characterized by comprising program status word holding means for holding a program status word including an indicating information indicating whether or not the instruction interval is to be sequentially executed and a control information showing an execution status of a program and instruction execution sequencing indication means responsive to said indicating information of said program status word held in said program status word holding means to give said instruction execution control portion an indication whether or not said instruction interval is to be sequentially executed.
Claim 3
Dependent Claim 76 words
The instruction execution control system claimed in claim 1, characterized by that said instruction execution sequencing indication means comprises setting means responsive to an instruction from said instruction execution control portion to set said indicating information of said program status word holding means so as to sequentially execute said instruction interval and resetting means resonsive to an indication from said instruction execution control portion so as to reset said indicating information set by said setting means.

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