US5670897A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed mask register for a configurable cellular array
Assignee: Xilinx Inc
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Filing: 1996-08-27
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Granted: 1997-09-23
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Expires: 2016-08-27
Abstract
Abstract An field programmable gate array (FPGA) of cells arranged in rows and columns is interconnected by a hierarchical routing structure. Switches separate the cells into blocks and into blocks of blocks with routing lines interconnecting the switches to form the hierarchy. Also, select units for allowing memory bits to be addressed both individually and in large and arbitrary groups are disclosed. Further a control store for configuring the FPGA is addressed as an SRAM and can be dynamically reconfigured during operation.
Inventors
- 👤 Thomas A. Kean
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:36
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1737; G; G06; G06F; G06F30/00; G06F30/30; G06F30/34; H03K19/177; H03K19/17704; H03K19/17748; H03K19/17752; H03K19/17756; H03K19/17758
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
114 words
A register structure comprising: a plurality of input lines; a mask register having one bit for each input line; a plurality of output lines; a matrix of programmable connectors for programmably connecting each of said input lines to each of said output lines; for each of said programmable connectors, a decoder receiving an enable signal from a corresponding bit in said mask register and a decode address signal derived from all less significant bits in said mask register, each of said decoders enabling a corresponding input line to be connected to a corresponding output line only when said decode address signal indicates that no previous input lines have been connected to that output line.
Claim 2
Dependent Claim
114 words
A register structure comprising: a plurality of input lines; a mask register having one bit for each input line; a plurality of output lines; a matrix of programmable connectors for programmably connecting each of said input lines to each of said output lines; for each of said programmable connectors, a decoder receiving an enable signal from a corresponding bit in said mask register and a decode address signal derived from all less significant bits in said mask register, each of said decoders enabling a corresponding input line to be connected to a corresponding output line only when said decode address signal indicates that no previous input lines have been connected to that output line.
Claim 3
Dependent Claim
22 words
A register structure as in claim 1 further comprising for each mask register bit an increment register for generating said decode address.
Claim 4
Dependent Claim
114 words
A register structure comprising: a plurality of input lines; a mask register having one bit for each input line; a plurality of output lines; a matrix of programmable connectors for programmably connecting each of said input lines to each of said output lines; for each of said programmable connectors, a decoder receiving an enable signal from a corresponding bit in said mask register and a decode address signal derived from all more significant bits in said mask register, each of said decoders enabling a corresponding input line to be connected to a corresponding output line only when said decode address signal indicates that no previous input lines have been connected to that output line.
Claim 5
Dependent Claim
114 words
A register structure comprising: a plurality of input lines; a mask register having one bit for each input line; a plurality of output lines; a matrix of programmable connectors for programmably connecting each of said input lines to each of said output lines; for each of said programmable connectors, a decoder receiving an enable signal from a corresponding bit in said mask register and a decode address signal derived from all more significant bits in said mask register, each of said decoders enabling a corresponding input line to be connected to a corresponding output line only when said decode address signal indicates that no previous input lines have been connected to that output line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-22 | 2001-03-24 | 2001-09-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-22 | 2005-03-24 | 2005-09-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-22 | 2009-03-24 | 2009-09-23 | $7700.00 | Window Closed / Lapsed |