US5637534A — Method of manufacturing semiconductor device havi…

Claim 1

Independent Claim 178 words

A method of manufacturing a semiconductor device having a multilevel interconnection structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate having a main surface on which said lower wiring layer is formed, and a via hole formed in said insulating interlayer, the method comprising: providing an atmosphere containing either a carbonless, chlorine-based gas, or a mixture of a carbonless, chlorine-based gas and an inactive gas; setting a flow rate ratio in which a flow rate of said chlorine-based gas divided by a sum of said chlorine-based gas flow rate and a flow rate of said inactive gas is such that contaminants that would otherwise promote deposition of Al on the insulating interlayer in a selective Al chemical vapor deposition (CVD) process can be effectively removed; plasma etching at least one surface of said insulating interlayer in said atmosphere to effectively remove said contaminants; and filling said via hole to form a via plug comprising a conductive material that includes one of Al and an Al alloy by the selective Al CVD process.

Claim 2

Independent Claim 178 words

A method of manufacturing a semiconductor device having a multilevel interconnection structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate having a main surface on which said lower wiring layer is formed, and a via hole formed in said insulating interlayer, the method comprising: providing an atmosphere containing either a carbonless, chlorine-based gas, or a mixture of a carbonless, chlorine-based gas and an inactive gas; setting a flow rate ratio in which a flow rate of said chlorine-based gas divided by a sum of said chlorine-based gas flow rate and a flow rate of said inactive gas is such that contaminants that would otherwise promote deposition of Al on the insulating interlayer in a selective Al chemical vapor deposition (CVD) process can be effectively removed; plasma etching at least one surface of said insulating interlayer in said atmosphere to effectively remove said contaminants; and filling said via hole to form a via plug comprising a conductive material that includes one of Al and an Al alloy by the selective Al CVD process.

Claim 3

Dependent Claim 29 words

A method according to claim 1, wherein the contaminants include chlorine-based residue, and the etching comprises weakening bonds between said chlorine-based residue and said surface of said insulating interlayer.

Claim 4

Dependent Claim 52 words

A method according to claim 2, further comprising heating the semiconductor substrate after plasma etching and prior to the filling in an atmosphere containing either a vacuum or at least one of an inactive gas and a reducing gas, thereby removing said weakened chlorine-based residue from said surface of said insulating interlayer.

Claim 5

Dependent Claim 13 words

A method according to claim 3, wherein said atmosphere contains H 2 .

Claim 6

Dependent Claim 28 words

A method according to claim 3, wherein a surface temperature of the substrate during said heating is higher than the substrate temperature during said selective Al CVD process.

Claim 7

Dependent Claim 21 words

A method according to claim 3, wherein an ultra-violet light is radiated to a surface of the substrate during said heating.

Claim 8

Dependent Claim 12 words

A method according to claim 1, wherein the inactive gas is He.

Claim 9

Dependent Claim 18 words

A method according to claim 1, wherein the plasma etching atmosphere contains BCl 3 as the chlorine-based gas.

Claim 10

Dependent Claim 19 words

A method according to claim 8, wherein the etching occurs in an atmosphere consisting essentially of BCl 3 .

Claim 11

Dependent Claim 36 words

A method according to claim 8, further comprising setting a ratio in which a total gas flow rate (sccm) divided by a total pressure (torr) of the atmosphere ranges from about 600 to about 2000 sccm/torr.

Claim 12

Dependent Claim 34 words

A method according to claim 8, further comprising setting a ratio in which a flow rate (sccm) of said chlorine-based gas divided by a volume (liter) of an etching chamber is about 4 sccm/liter.

Claim 13

Dependent Claim 41 words

A method according to claim 1, wherein the flow rate ratio is a volumetric flow rate ratio, the plasma etching atmosphere is a gas containing BCl 3 and Ar, and said volumetric flow rate ratio is BCl 3 /(BCl 3 +Ar)>0.36.

Claim 14

Dependent Claim 41 words

A method according to claim 12, wherein the flow rate ratio is a volumetric flow rate ratio, the plasma etching atmosphere is a gas containing BCl 3 and Ar, and said volumetric flow rate ratio is BCl 3 /(BCl 3 +Ar)>0.63.

Claim 15

Dependent Claim 39 words

A method according to claim 13, wherein the flow rate ratio is a volumetric flow rate ratio, the plasma etching atmosphere is a gas containing BCl 3 and Ar, and said volumetric flow rate ratio is BCl.sub.3 /(BCl.sub.3 +Ar)≧0.82.

Claim 16

Dependent Claim 39 words

A method according to claim 1, wherein the plasma etching atmosphere is a gas mixture containing BCl 3 and Cl 2 , and a volumetric flow rate ratio of chlorine-based components is BCl 3 /(BCl 3 +Cl 2 )≧0.25.

Claim 17

Dependent Claim 40 words

A method according to claim 15, wherein the plasma etching atmosphere is a gas mixture containing BCl 3 and Cl 2 , and said volumetric flow rate ratio of said chlorine-based components is BCl 3 /(BCl 3 +Cl 2 )≧0.75.

Claim 18

Dependent Claim 24 words

A method according to claim 1, wherein said lower wiring layer comprises an Al containing film including one of Al and an Al alloy.

Claim 19

Dependent Claim 66 words

A method according to claim 17, wherein the contaminants include organic contaminants, and a part of the Al containing film located in a bottom portion of said via hole is exposed before the plasma etching and, wherein the plasma etching removes an alumina film formed on a surface of the Al containing film, and removes said organic contaminants attached to the surface of the insulating interlayer.

Claim 20

Dependent Claim 30 words

A method according to claim 18, wherein said lower wiring layer has a multilayered structure, and at least a top layer of the multilayered structure is the Al containing film.

Claim 21

Dependent Claim 78 words

A method according to claim 18, further comprising depositing a metal film including one of a high melting point metal and a high melting point metal compound on the Al containing film, forming the lower wiring layer by removing portions of said metal film and said Al containing film; and removing a part of said metal film located in the bottom portion of said via hole, and exposing a part of said Al film before the plasma etching.

Claim 22

Dependent Claim 52 words

A method according to claim 18, wherein the plasma etching includes etching a surface of said Al containing film exposed in the bottom portion of said via hole into a concave shape, and forming a diameter of a region etched to the concave shape greater than a diameter of the via hole.

Claim 23

Dependent Claim 70 words

A method according to claim 17, further comprising depositing a metal film including one of a high melting point metal and high melting point metal compound on the Al film; forming the lower wiring layer by removing portions of said metal, film and said Al containing film; and plasma etching a bottom portion of said via hole where said metal film is exposed, and the surface of said insulating interlayer.

Claim 24

Dependent Claim 12 words

A method according to claim 22, wherein said metal film includes Ti.

Claim 25

Dependent Claim 18 words

A method according to claim 22, wherein said metal film includes one of titanium nitride and titanium oxynitride.

Claim 26

Dependent Claim 37 words

A method according to claim 22, wherein the plasma etching further comprises removing a part of said metal film located in the bottom portion of the via hole, and exposing a part of said Al containing film.

Claim 27

Dependent Claim 65 words

A method according to claim 1, further comprising forming an upper wiring layer on a surface of the insulating interlayer where the via plug is formed in the via hole, said forming comprising: 1) sputtering an Al containing film including one of Al and an Al alloy, and 2) heating the semiconductor substrate where said Al containing film is sputtered to at least 400° C.

Claim 28

Dependent Claim 33 words

A method according to claim 26, further comprising maintaining the semiconductor substrate in an airless environment during a time spanning said filling of said via hole and said heating of the semiconductor substrate.

Claim 29

Dependent Claim 38 words

A method according to claim 27, wherein said forming further comprises depositing an underlying film including one of Ti, Zr, Hf, Ti silicide, Zr silicide, Hf silicide, Si, Ge and Cu, prior to sputtering the Al containing film.

Claim 30

Dependent Claim 14 words

A method according to claim 28, wherein said underlying film is a Ti film.

Claim 31

Dependent Claim 19 words

A method according to claim 1, wherein a diameter of said via hole is no greater than 0.8 μm.

Claim 32

Dependent Claim 19 words

A method according to claim 6, wherein the diameter of said via hole is no greater than 0.5 μm.

Claim 33

Dependent Claim 22 words

A method according to claim 1, wherein a sectional area of said via hole is no greater than 0.5 μm 2 .

Claim 34

Dependent Claim 22 words

A method according to claim 32, wherein the sectional area of said via hole is no greater than 0.2 μm 2 .

Claim 35

Dependent Claim 40 words

A method according to claim 1, further comprising forming an upper wiring layer comprising an Al containing film including one of Al and an Al alloy on the insulating interlayer where the via plug is formed in the via hole.

Claim 36

Dependent Claim 28 words

A method according to claim 34, wherein forming said upper wiring layer further comprises sputtering the Al containing film directly to the upper surface of said via plug.

Claim 37

Dependent Claim 34 words

A method according to claim 35, further comprising maintaining the semiconductor substrate in an airless environment during a time spanning said filling of said via hole and said sputtering of said Al containing film.

Claim 38

Dependent Claim 51 words

A method according to claim 1, further comprising forming an upper wiring layer by sputtering an Al containing film including one of Al and an Al alloy while maintaining a surface temperature of said semiconductor substrate at at least 300° C. after the via plug is formed in the via hole.

Claim 39

Dependent Claim 34 words

A method according to claim 37, further comprising maintaining the semiconductor substrate in an airless environment during a time spanning said filling of said via hole and said sputtering of said Al containing film.

Claim 40

Dependent Claim 42 words

A method according to claim 37, wherein forming said upper wiring layer further comprises depositing an underlying metal film including one of Ti, Zr, Hf, Ti silicide, Zr silicide, Hf silicide, Si, Ge and Cu, prior to sputtering the Al containing film.

Claim 41

Dependent Claim 14 words

A method according to claim 39, wherein said underlying film is a Ti film.

Claim 42

Dependent Claim 23 words

A method according to claim 1, wherein said flow rate ratio is a volumetric flow rate ratio set at greater than about 0.36.

Claim 43

Dependent Claim 23 words

A method according to claim 1, wherein said flow rate ratio is a volumetric flow rate ratio set at greater than about 0.63.

Claim 44

Dependent Claim 24 words

A method according to claim 1, wherein said flow rate ratio is a volumetric flow rate ratio set at not less than about 0.82.

Claim 45

Dependent Claim 21 words

A method according to claim 1, wherein said etching includes etching in an atmosphere consisting essentially of a carbonless, chlorine-based gas.

Claim 46

Dependent Claim 23 words

A method according to claim 1, wherein the flow rate ratio is a mass flow rate ratio set at greater than about 0.62.

Claim 47

Dependent Claim 23 words

A method according to claim 1, wherein the flow rate ratio is a mass flow rate ratio set at greater than about 0.83.

Claim 48

Dependent Claim 24 words

A method according to claim 1, wherein the flow rate ratio is a mass flow rate ratio set at not less than about 0.93.

Claim 49

Dependent Claim 36 words

A method according to claim 1, further comprising setting a ratio in which a total gas flow rate (sccm) divided by a total pressure (torr) of the atmosphere ranges from about 600 to about 2000 sccm/torr.

Claim 50

Independent Claim 135 words

A method of manufacturing a semiconductor device having a multilevel interconnection structure, comprising: forming at least one via hole in an insulating interlayer that is formed on a lower wiring layer, which, in turn, is formed over a semiconductor substrate; at least partially filling the via hole by performing selective chemical vapor deposition to form a via plug comprising a conductive material including one of Al and an Al alloy that electrically connects with the lower wiring layer; and forming an upper wiring layer on a surface of the insulating interlayer where the via plug is formed in the via hole, by sputtering an Al containing film including one of Al and an Al alloy, while maintaining a surface temperature of said semiconductor substrate at at least 300° C. when sputtering the Al containing film.

Claim 51

Independent Claim 135 words

A method of manufacturing a semiconductor device having a multilevel interconnection structure, comprising: forming at least one via hole in an insulating interlayer that is formed on a lower wiring layer, which, in turn, is formed over a semiconductor substrate; at least partially filling the via hole by performing selective chemical vapor deposition to form a via plug comprising a conductive material including one of Al and an Al alloy that electrically connects with the lower wiring layer; and forming an upper wiring layer on a surface of the insulating interlayer where the via plug is formed in the via hole, by sputtering an Al containing film including one of Al and an Al alloy, while maintaining a surface temperature of said semiconductor substrate at at least 300° C. when sputtering the Al containing film.

Claim 52

Dependent Claim 34 words

A method according to claim 49, further comprising maintaining the semiconductor substrate in an airless environment during a time spanning said filling of said via hole and said sputtering of said Al containing film.

Claim 53

Dependent Claim 41 words

A method according to claim 49, wherein the upper wiring layer forming further comprises depositing an underlying film including one of Ti, Zr, Hf, Ti silicide, Zr silicide, Hf silicide, Si, Ge and Cu, prior to sputtering the Al containing film.

Claim 54

Dependent Claim 38 words

A method accordingly to claim 51, wherein said underlying film is a titanium film and is deposited directly on an upper surface of the via plug, and said Al containing film is sputtered directly on the underlying film.

Claim 55

Dependent Claim 34 words

A method according to claim 52, wherein the semiconductor substrate is kept in an airless environment during a time spanning said filling of the via hole and said sputtering of the Al containing film.

Claim 56

Dependent Claim 22 words

A method according to claim 49, wherein said Al containing film is directly sputtered on an upper surface of the via plug.

Claim 57

Dependent Claim 24 words

A method according to claim 49, wherein said forming includes sputtering said Al containing film directly on said via plug and said insulating interlayer.

Claim 58

Dependent Claim 97 words

A method according to claim 49, wherein: said forming the at least one via hole further comprises forming at least two via holes having different depths; said filling includes filling the at least two via holes to form at least two via plugs in said at least two via holes such that a top of the via plug in the deepest via hole is lower than the surface of the insulating interlayer; and said sputtering forms the Al containing film such that an upper portion of the deepest via hole is filled with the Al containing film.

Claim 59

Independent Claim 129 words

A method of manufacturing a semiconductor device having a multilevel interconnection structure, comprising: forming at least one via hole in an insulating interlayer that is formed on a lower wiring layer, which, in turn, is formed over a semiconductor substrate; at least partially filling the via hole by performing selective chemical vapor deposition to form a via plug comprising a conductive material including one of Al and an Al alloy; forming an upper wiring layer on a surface of the insulating interlayer where the via plug is formed in the via hole, said forming an upper wiring layer comprising sputtering an Al containing film including one of Al and an Al alloy, and heating the semiconductor substrate where said Al containing film is sputtered to at least 400° C.

Claim 60

Independent Claim 129 words

A method of manufacturing a semiconductor device having a multilevel interconnection structure, comprising: forming at least one via hole in an insulating interlayer that is formed on a lower wiring layer, which, in turn, is formed over a semiconductor substrate; at least partially filling the via hole by performing selective chemical vapor deposition to form a via plug comprising a conductive material including one of Al and an Al alloy; forming an upper wiring layer on a surface of the insulating interlayer where the via plug is formed in the via hole, said forming an upper wiring layer comprising sputtering an Al containing film including one of Al and an Al alloy, and heating the semiconductor substrate where said Al containing film is sputtered to at least 400° C.

Claim 61

Dependent Claim 33 words

A method according to claim 57, further comprising maintaining the semiconductor substrate in an airless environment during a time spanning said filling of the via hole and said heating of the semiconductor substrate.

Claim 62

Dependent Claim 41 words

A method according to claim 57, wherein the upper wiring layer forming further comprises depositing an underlying film including one of Ti, Zr, Hf, Ti silicide, Zr silicide, Hf silicide, Si, Ge and Cu, prior to sputtering the Al containing film.

Claim 63

Dependent Claim 38 words

A method according to claim 59, wherein said underlying film is a titanium film and is deposited directly on an upper surface of the via plug, and said Al containing film is sputtered directly on the underlying film.

Claim 64

Dependent Claim 33 words

A method according to claim 60, wherein the semiconductor substrate is kept in an airless environment during a time spanning said filling of the via hole and said heating of the semiconductor substrate.

Claim 65

Dependent Claim 22 words

A method according to claim 57, wherein said Al containing film is directly sputtered on an upper surface of the via plug.

Claim 66

Dependent Claim 24 words

A method according to claim 57, wherein said forming includes sputtering said Al containing film directly on said via plug and said insulating interlayer.

Claim 67

Dependent Claim 104 words

A method according to claim 57, wherein: said forming the at least one via hole further comprises forming at least two via holes having different depths; said filling includes filling the at least two via holes to form at least two via plugs in said at least two via holes such that a top of the via plug in the deepest via hole is lower than the surface of the insulating interlayer; and said heating makes the Al containing film to flow into the deepest via hole such that an upper portion of the deepest via hole is filled with the Al containing film.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-06-09	2000-12-09	2001-06-10	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-06-09	2004-12-09	2005-06-10	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-06-09	2008-12-09	2009-06-10	$7700.00	Window Closed / Lapsed

Method of manufacturing semiconductor device having multilevel interconnection structure

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