Serializer circuit for loading and shifting out digitized analog signals

Claim 2

A serializer circuit for loading and shifting out multiple packets of digitized analog signals, comprising: translation circuitry for translating an analog signal into a digital representation of said analog signal, said digital representation comprising a plurality of binary bit positions; a register for receiving, shifting and loading said digital representations; load/shift control circuitry for loading said digital representations into said register and for serially shifting said digital representations out of said register; a receiver circuit for serially receiving multiple packets of said digital representations of said digitized analog signals from said register; said translation circuitry comprising circuitry for translating said analog signal into said digital representation while said load/shift control circuitry continuously loads and shifts said register to output a plurality of digital representations of said translated analog signals; said receiver circuit comprising a receive register for receiving and storing a predetermined number of serial data bit positions and a parallel memory for storing the contents of said register; and further comprising control circuitry for storing the contents of said receive register into said parallel memory without interrupting the operation of said receiver circuit.

Claim 3

The serializer circuit of claim 1, further comprising circuitry for selectively shifting said serial shifted digital representations from said serializer circuit to said receiver circuit either directly or through a plurality of predetermined circuits, said predetermined circuits positioned on a serial path between said serializer circuit and said receiver circuit.

Claim 4

The serializer circuit of claim 1, further comprising circuitry for delaying said receiving and storing operation of said receiver register until said serial data bit positions pass through a predetermined number of intermediate circuits and are serially input to said receiver circuit.

Claim 5

The serializer circuit of claim 1, further comprising circuitry for testing whether said analog signals fall within a predetermined range.

Claim 6

A transmitter test circuit controlled by a serial bus for serially transmitting multiple packets of digital representations of analog signal measurements, comprising: an analog to digital interface circuit for receiving analog signals and outputting digital representations of said analog signals; a sample register enabled by control inputs from said serial bus for receiving and shifting out said digital representations; a serializer circuit associated with said sample register, said serializer circuit further comprising a control circuit for loading said digital representations into said sample register and shifting said digital representations from said sample register, and a counter circuit for counting the number of shifting operations performed in said sample register before the next load operation can occur, said loading and shifting of said digital representations occurring cyclically once enabled by said control inputs from said serial bus.

Claim 7

A transmitter test circuit controlled by a serial bus for serially transmitting multiple packets of digital representations of analog signal measurements, comprising: an analog to digital interface circuit for receiving analog signals and outputting digital representations of said analog signals; a sample register enabled by control inputs from said serial bus for receiving and shifting out said digital representations; a serializer circuit associated with said sample register, said serializer circuit further comprising a control circuit for loading said digital representations into said sample register and shifting said digital representations from said sample register, and a counter circuit for counting the number of shifting operations performed in said sample register before the next load operation can occur, said loading and shifting of said digital representations occurring cyclically once enabled by said control inputs from said serial bus.

Claim 8

The transmitter test circuit of claim 5, further comprising a load/shift control multiplexer associated with said serializer circuit for selectively controlling inputs to said sample register, said load/shift control multiplexer associated to receive selection control input to control the digital representation flow into said sample register.

Claim 9

The transmitter test circuit of claim 5, wherein said sample register selectively permits compressing multiple parallel flow of said digital representations into said sample register.

Claim 10

The transmitter test circuit of claim 5, further comprising a test bus controller for receiving serial data from and outputting serial data to said serializer circuit.

Claim 11

The transmitter test circuit of claim 8, wherein said test bus controller is associated with a memory for storing a plurality of test programs and storing a plurality of said digital representations from said transmitter circuit.

Claim 12

The transmitter test circuit of claim 9, further comprising a processor associated with said memory and said test bus controller for executing a plurality of said stored test programs.

Claim 13

A transmitter test circuit controlled by a serial bus for serially transmitting multiple packets of digital representations of analog signal measurements, comprising; an analog to digital interface circuit for receiving analog signals and outputting digital representations of said analog signals; a sample register enabled by control inputs from said serial bus for receiving and shifting out said digital representations; a serializer circuit associated with said sample register, said serializer circuit further comprising a control circuit for loading said distal representations into said sample register and shifting said digital representations from said sample register, and a counter circuit for counting the number of shifting operations performed in said sample register before the next load operation can occur, said loading and shifting of said digital representations occurring cyclically once enabled by said control inputs from said serial bus; and a test bus controller coupled to said serial bus, wherein said test bus controller comprises: input/output circuitry; a memory; a serial input parallel output register; a parallel input serial output register; a test port controller circuit; a processor wherein said processor couples to said memory and said input/output circuitry for controlling operations of said memory and said input/output circuitry, said memory providing storage for a plurality of test programs executed by said processor and further serving as storage for test data from said sample register and said serializer circuit, said input/output circuitry for allowing said test bus controller to communicate to a plurality of external integrated circuits; said serial input parallel output register for receiving control input from said test port controller and serial data input from said sample register and said serializer circuit and outputting parallel data to said processor; and wherein said parallel input serial output register receives parallel data and input from said processor and control input from said test port controller and outputs serial data to said sample register and said serializer circuit, and further wherein said test port controller receives control input from said processor and outputs control to said serial input parallel output register, outputs control to said parallel input serial output register, outputs status information to said processor, and outputs control signals to said sample register and said serializer circuit.

Claim 14

A transmitter test circuit controlled by a serial bus for serially transmitting multiple packets of digital representations of analog signal measurements, comprising; an analog to digital interface circuit for receiving analog signals and outputting digital representations of said analog signals; a sample register enabled by control inputs from said serial bus for receiving and shifting out said digital representations; a serializer circuit associated with said sample register, said serializer circuit further comprising a control circuit for loading said distal representations into said sample register and shifting said digital representations from said sample register, and a counter circuit for counting the number of shifting operations performed in said sample register before the next load operation can occur, said loading and shifting of said digital representations occurring cyclically once enabled by said control inputs from said serial bus; and a test bus controller coupled to said serial bus, wherein said test bus controller comprises: input/output circuitry; a memory; a serial input parallel output register; a parallel input serial output register; a test port controller circuit; a processor wherein said processor couples to said memory and said input/output circuitry for controlling operations of said memory and said input/output circuitry, said memory providing storage for a plurality of test programs executed by said processor and further serving as storage for test data from said sample register and said serializer circuit, said input/output circuitry for allowing said test bus controller to communicate to a plurality of external integrated circuits; said serial input parallel output register for receiving control input from said test port controller and serial data input from said sample register and said serializer circuit and outputting parallel data to said processor; and wherein said parallel input serial output register receives parallel data and input from said processor and control input from said test port controller and outputs serial data to said sample register and said serializer circuit, and further wherein said test port controller receives control input from said processor and outputs control to said serial input parallel output register, outputs control to said parallel input serial output register, outputs status information to said processor, and outputs control signals to said sample register and said serializer circuit.

Claim 17

The method of claim 12, further comprising the step of translating said analog signals into said digital representations while continuously loading and shifting out a plurality of previously translated analog signals from said transmit register.

Claim 18

The method of claim 12, further comprising the step of selectively shifting said digital representations from said transmit register either directly or through a plurality of predetermined circuits in a serial path between said transmit register and said receive register.

Claim 19

The method of claim 12, further comprising the step of delaying shifting of said digital representations into said receive register until said predetermined number of serial data bit positions pass through a predetermined number of intermediate circuits and are serially input into said receive register.

Claim 20

The method of claim 12, further comprising the step of testing whether said received analog signals fall within a predetermined range of values.

Claim 23

The method of claim 17, further comprising the step of selectively controlling the loading of said digital representations into said sample register using a load data multiplexer.

Claim 24

The method of claim 17, further comprising the step of loading a single parallel flow of said digital representations into said sample register.

Claim 25

The method of claim 19, further comprising the step of selectively compressing multiple parallel flows of said digital representations into said sample register.

Claim 26

The method of claim 17, further comprising the steps of storing a plurality of test programs in a memory and storing a plurality of digital representations from said sample register in said memory.

Claim 27

The method of claim 21, further comprising the steps of executing a plurality of said test programs in a processor and receiving a plurality of test data inputs in response, said processor subsequently being used to test the plurality of received test data inputs to determine if the received test data inputs fall within an anticipated range.

Claim 28

A test system for testing an analog circuit, comprising; a transmitter circuit associated with an analog circuit to be tested and operable to receive and measure analog signal input from the analog circuit for translating a plurality of individual analog signal measurements into a plurality of associated individual digital representations and for continuously outputting a plurality of packets of said digital representations in a serial bit format; a receiver circuit coupled to said transmitter circuit for continuously receiving a plurality of said digital representations in said serial bit format from said transmitter circuit, for storing each received serial bit format into a memory, and for processing the stored plurality of serial bit formats of said digital representations of said analog signal measurements for testing of the analog circuit; and further comprising circuitry for coupling said receiver circuit to a plurality of ones of said transmitter circuit.

Claim 29

A test system for testing an analog circuit, comprising; a transmitter circuit associated with an analog circuit to be tested and operable to receive and measure analog signal input from the analog circuit for translating a plurality of individual analog signal measurements into a plurality of associated individual digital representations and for continuously outputting a plurality of packets of said digital representations in a serial bit format; a receiver circuit coupled to said transmitter circuit for continuously receiving a plurality of said digital representations in said serial bit format from said transmitter circuit, for storing each received serial bit format into a memory, and for processing the stored plurality of serial bit formats of said digital representations of said analog signal measurements for testing of the analog circuit; and further comprising circuitry for coupling said receiver circuit to a plurality of ones of said transmitter circuit.

Claim 30

The test system of claim 23, further comprising a serial bus for coupling said transmitter circuit to at least one of a plurality of ones of said receiver circuit.

Claim 31

The test system of claim 23, wherein said transmitter circuit comprises an integrated circuit.

Claim 32

The test system of claim 23, wherein said transmitter circuit comprises a sub-circuit within an integrated circuit.