US4639664A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for testing a plurality of integrated circuits in parallel
Assignee: Texas Instruments Inc
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Filing: 1984-05-31
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Granted: 1987-01-27
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Expires: 2004-05-31
Abstract
Abstract In accordance with a broad aspect of the invention, a system is presented for parametrically and functionally testing integrated circuit devices in parallel. At least one integrated circuit device receiving channel is provided for defining a plurality of integrated circuit device test stations therealong, and means are provided for delivering parametric and functional test signals at least functionally in parallel to each of the integrated circuit device test stations. Means are provided at each test station for selectively engaging the integrated circuit devices to apply the parametric and functional test signals to the integrated circuit device at that station, and to selectively isolate the device from the test signals. Means are provided for receiving an output from each test location in response to the test signals, and means for determining from the output the parameters of each tested integrated circuit device. In accordance with the invention, means are provided for sorting the tested integrated circuit devices according to their measured or tested parameters.
Inventors
- 👤 Anthony M. Chiu
- 👤 Mark D. Allison
- 👤 James W. Jones
- 👤 Lyndale A. Trammell
- 👤 Fock San Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:54
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/316
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
140 words
Apparatus for parametrically and functionally testing integrated circuit devices in parallel, comprising: at least one integrated circuit receiving channel defining a plurality of integrated circuit device test stations therealong; load means for automatically delivering via the integrated circuit receiving channel to each of the plurality of integrated circuit device test stations a separate integrated circuit device for testing; means for delivering parametric and functional test signals at least functionally in parallel to each of said integrated circuit device test stations; means at each of said test stations for selectively engaging the delivered integrated circuit device to apply the parameter test signals to the integrated circuit device at said test station; means for receiving an output from each test location in response to the test signals; and means for determining from said output the parameters of each tested integrated circuit device.
Claim 2
Dependent Claim
140 words
Apparatus for parametrically and functionally testing integrated circuit devices in parallel, comprising: at least one integrated circuit receiving channel defining a plurality of integrated circuit device test stations therealong; load means for automatically delivering via the integrated circuit receiving channel to each of the plurality of integrated circuit device test stations a separate integrated circuit device for testing; means for delivering parametric and functional test signals at least functionally in parallel to each of said integrated circuit device test stations; means at each of said test stations for selectively engaging the delivered integrated circuit device to apply the parameter test signals to the integrated circuit device at said test station; means for receiving an output from each test location in response to the test signals; and means for determining from said output the parameters of each tested integrated circuit device.
Claim 3
Dependent Claim
21 words
The apparatus of claim 1 further comprising means for sorting said integrated circuit devices in accordance with said determined output parameters.
Claim 4
Dependent Claim
22 words
The apparatus of claim 1 wherein said at least one parallel integrated circuit device receiving channel is a plurality of parallel tracks.
Claim 5
Dependent Claim
20 words
The apparatus of claim 1 wherein said at least one parallel integrated circuit device receiving channel is two parallel tracks.
Claim 6
Dependent Claim
13 words
The apparatus of claim 4 wherein said two tracks comprise four test stations.
Claim 7
Dependent Claim
21 words
The apparatus of claim 5 wherein said four test stations are symetrically located to minimize differences in input signal paths therebetween.
Claim 8
Dependent Claim
19 words
The apparatus of claim 1 further comprising means for maintaining each of the test stations at the same temperature.
Claim 9
Dependent Claim
33 words
The apparatus of claim 7 wherein said temperature maintaining means comprises a source of air at a desired test temperature and a plenum for distributing the air at least onto the test stations.
Claim 10
Dependent Claim
59 words
The apparatus of claim 1 wherein said means at each test station for selectively engaging said integrated circuit devices comprises: a guide bar on which are carried at least two integrated circuit devices; a plurality of integrated circuit device contacting members; and means for moving said device contacting members between engaging and disengaging positions of said integrated circuit devices.
Claim 11
Dependent Claim
25 words
The apparatus of claim 1 wherein the load means comprises an input shuttle to alternately load devices into the respective parallel integrated circuit receiving channels.
Claim 12
Dependent Claim
47 words
The apparatus of claim 2 wherein said means for sorting comprises: a queue; a shuttle to receive devices from said queue, and a plurality of bins over which said shuttle travels to dispense said integrated circuits into selected ones of said bins according to the test measurements.
Claim 13
Independent Claim
100 words
A method of testing integrated circuit devices, comprising: automatically delivering to each member of a plurality of parallel connected integrated circuit test stations a separate integrated circuit device for testing: providing parametric and functional test signals to the plurality of integrated circuit device test stations and to each delivered integrated circuit device thereby, monitoring output signals produced from each device in response to said test signals, selectively isolating a set of integrated circuit devices when the monitored output signals indicate a device has failed, and repeating said test steps of providing, monitoring and isolating until the failing device is identified.
Claim 14
Independent Claim
100 words
A method of testing integrated circuit devices, comprising: automatically delivering to each member of a plurality of parallel connected integrated circuit test stations a separate integrated circuit device for testing: providing parametric and functional test signals to the plurality of integrated circuit device test stations and to each delivered integrated circuit device thereby, monitoring output signals produced from each device in response to said test signals, selectively isolating a set of integrated circuit devices when the monitored output signals indicate a device has failed, and repeating said test steps of providing, monitoring and isolating until the failing device is identified.
References Cited (Backward Citations)
US4509008A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-01-26 | 1990-07-28 | 1991-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-01-26 | 1994-07-28 | 1995-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-01-26 | 1998-07-28 | 1999-01-27 | $7700.00 | Window Closed / Lapsed |