Serial scan diagnostics apparatus and method for a memory device

Claim 2

In a memory integrated circuit for storing a plurality of bits in a memory array having a plurality of memory locations, apparatus for performing scan diagnostics comprising: an input register for receiving signals in parallel; an output register for outputting signals in parallel; a memory control means coupled to a memory array and coupled to said input register and said output register; a shift register for receiving as input at least one of three data inputs, said three data inputs being a serial data stream, parallel data from said input buffer and parallel data from said output buffer and for outputting at least one of three outputs, said three outputs being a serial data stream, parallel data output to said input register, and parallel data output to said output register.

Claim 3

Apparatus, as claimed in claim 1, wherein said memory array and said shift register are formed on a single integrated circuit chip.

Claim 4

Apparatus, as claimed in claim 1, wherein said shift register has a parallel input means and a serial output means, and further comprising: bus means coupling said input register to said shift register and to said memory control for permitting receipt of at least some of said input signals in both of said shift register and said memory control means in parallel; and means for serially outputting said input signals onto said serial output line of said shift register to provide a scan-out of the state of the input register.

Claim 5

Apparatus, as claimed in claim 3, wherein said input signals output on said output line include all of the input signals received in said input register.

Claim 6

Apparatus, as claimed in claim 3, wherein said memory array is coupled to a diagnostics processor and further comprising means for conveying said input signals to said diagnostics processor.

Claim 7

Apparatus, as claimed in claim 3, wherein said receipt in said shift register and said memory control is substantially simultaneous.

Claim 8

Apparatus, as claimed in claim 1, wherein said shift register has a serial input line and a parallel output line, said parallel output line being coupled to said input register, and further comprising: means for serially receiving a plurality of input signals onto said serial input line of said shift register and shifting said input signals into said shift register; means for outputting said input signals from said shift register onto said output line in parallel for receipt by said input register to force the state of said input register.

Claim 9

Apparatus, as claimed in claim 7, wherein all of said input signals during at least one memory cycle are received in said input buffer from said means for outputting.

Claim 10

Apparatus, as claimed in claim 7, wherein said plurality of input signals is generated by a pseudo-random generator.

Claim 11

Apparatus, as claimed in claim 7, further comprising means for interrupting said means for serially receiving to permit execution of at least one memory cycle.

Claim 12

Apparatus, as claimed in claim 7, further comprising input multiplexer means for selectably providing said input signals on said output lines to said input register.

Claim 13

Apparatus, as claimed in claim 1, wherein said shift register has a serial input line and a parallel output line coupled to said output register and further comprising; means for serially receiving a plurality of output signals onto said input line of said shift register and shifting said output signals into said shift register; means for outputting said output signals from said shift register onto said output line in parallel for receipt by said output register, to force the state of the output register.

Claim 14

Apparatus, as claimed in claim 12, wherein all output signals received in said output register in at least a first memory cycle are received from said parallel output line of said shift register.

Claim 15

Apparatus, as claimed in claim 12, further comprising means for interrupting said means for serially receiving to permit execution of at least one memory cycle.

Claim 16

Apparatus, as claimed in claim 12, further comprising output multiplexer means for selectably providing said output signals on said output lines to said output register.

Claim 17

Apparatus, as claimed in claim 1, wherein said shift register has a parallel input and a serial output line, and further comprising; bus means coupling said output register to said shift register for permitting receipt of said output signals in said shift register in parallel; and means for serially outputting said output signals onto said output line of said shift register to provide a scan-out of the state of the output buffer.

Claim 18

Apparatus, as claimed in claim 16, wherein said output signals output on said output line include all of the output signals received in said output register.

Claim 19

In a memory system including at least a first integrated circuit having a memory array said memory system coupled to a parallel input bus, a shift register device for use in scan diagnostics, comprising: a plurality of two-phase latch portions, each portion comprising a first phase latch and a second phase latch coupled to said first phase latch and a multiplexer means for selecting the input for said second phase latch between a serial data source and a parallel data source; an input buffer for providing data in parallel to at least some of said plurality of latch portions; multiplexer means for selecting the input for said input buffer between said parallel input bus and at least some of said plurality of said second-phase latches; an output buffer for receiving data in parallel from at least some of said plurality of latch portions; multiplexer means for selecting the input for said output buffer between said memory array and at least some of said plurality of second-phase latches; means for serially receiving data into said latch portions; and means for serially outputting data from said latch portions.

Claim 20

In a memory system including at least a first integrated circuit having a memory array said memory system coupled to a parallel input bus, a shift register device for use in scan diagnostics, comprising: a plurality of two-phase latch portions, each portion comprising a first phase latch and a second phase latch coupled to said first phase latch and a multiplexer means for selecting the input for said second phase latch between a serial data source and a parallel data source; an input buffer for providing data in parallel to at least some of said plurality of latch portions; multiplexer means for selecting the input for said input buffer between said parallel input bus and at least some of said plurality of said second-phase latches; an output buffer for receiving data in parallel from at least some of said plurality of latch portions; multiplexer means for selecting the input for said output buffer between said memory array and at least some of said plurality of second-phase latches; means for serially receiving data into said latch portions; and means for serially outputting data from said latch portions.

Claim 21

Apparatus, as claimed in claim 18, further comprising: at least a second memory integrated circuit having a shift register with a serial input means; and means for coupling said means for serially outputting data from said latch portions of said first integrated circuit to said serial input means of said second memory integrated circuit.

Claim 22

In a memory integrated circuit for storing a plurality of bits in memory locations, a method for obtaining an indication of a plurality of input signals input to said integrated circuit comprising: providing an input register; receiving said plurality of input signals in said input register in a parallel fashion; providing a shift register having a parallel input and a serial output line; providing a memory control means coupled to a memory array; coupling said input register to said shift register and to said memory control for permitting receipt of said input signals in both of said shift register and said memory control means in parallel; serially outputting said input signals onto said output line of said shift register.

Claim 23

In a memory integrated circuit for storing a plurality of bits in memory locations, a method for obtaining an indication of a plurality of input signals input to said integrated circuit comprising: providing an input register; receiving said plurality of input signals in said input register in a parallel fashion; providing a shift register having a parallel input and a serial output line; providing a memory control means coupled to a memory array; coupling said input register to said shift register and to said memory control for permitting receipt of said input signals in both of said shift register and said memory control means in parallel; serially outputting said input signals onto said output line of said shift register.

Claim 24

In a memory integrated circuit for storing a plurality of bits in memory locations, a method for performing scan diagnostics comprising: providing an input register for receiving signals in parallel; providing an output register for outputting signals in parallel; providing a memory control means coupled to a memory array and coupled to said input register and said output register; providing a shift register having a parallel input, a serial input, a parallel output and a serial output; and receiving as input to said shift register, at least one of three data inputs, said three data inputs being a serial data stream, parallel data from said input buffer and parallel data from said output buffer and for outputting at least one of three outputs, said three outputs being a serial data stream parallel data output to said input register and parallel data output to said output register.

Claim 25

In a memory integrated circuit for storing a plurality of bits in memory locations, a method for performing scan diagnostics comprising: providing an input register for receiving signals in parallel; providing an output register for outputting signals in parallel; providing a memory control means coupled to a memory array and coupled to said input register and said output register; providing a shift register having a parallel input, a serial input, a parallel output and a serial output; and receiving as input to said shift register, at least one of three data inputs, said three data inputs being a serial data stream, parallel data from said input buffer and parallel data from said output buffer and for outputting at least one of three outputs, said three outputs being a serial data stream parallel data output to said input register and parallel data output to said output register.