US3863226A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Configurable communications controller having shared logic for providing predetermined operations
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1973-01-02
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Granted: 1975-01-28
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Expires: 1993-01-02
Abstract
Abstract The apparatus of the invention includes receive logic for converting serial bit characters to parallel bit characters and transmit logic for providing a parallel to serial bit character conversion. The receive and transmit logic are coupled between a processor and a communication line. Both the transmit and receive logic are coupled with a code unit which performs specified logic operations in response to the identity of the characters either received or transmitted. The apparatus is easily configurable for different bit length characters and the code unit is time-shared by the transmit and the receive logic.
Inventors
- 👤 Scott W Ryburn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:23
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/14; H04L5/16
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
279 words
Apparatus for transferring data charActers, each having a plurality of bits, between a data processor and a communication line, said apparatus comprising: A. receive logic for converting bit serial characters received from said line to bit parallel characters; B. transmit logic for converting bit parallel characters to bit serial characters for transfer over said lines; C. bit routing means included in both said receive logic and said transmit logic; D. a code unit coupled to receive bit parallel characters from said receive logic and from said transmit logic, said code unit comprising 1. means for detecting the identity of said characters; and 2. means for performing predetermined logic operations in response to the identity of certain ones of said characters; E. means for configuring said bit routing means included in said receive and transmit logic in order to adapt to a predetermined number of bits in said characters; F. means, included in the coupling between said code unit and said receive logic and said transmit logic, for enabling said code unit to be time shared between said receive logic and said transmit logic; and G. wherein said means for detecting comprises: 1. a comparator having first and second inputs; 2. means for selecting either said character from said receive logic or said character from said transmit logic for coupling to said first input; 3. means for providing a plurality of code characters; 4. means for sequentially selecting each of said plurality of code characters for coupling to said second input; and 5. means for indicating the identity of said characters provided by either said receive logic or said transmit logic when a positive comparison is made by said comparator.
Claim 2
Dependent Claim
279 words
Apparatus for transferring data charActers, each having a plurality of bits, between a data processor and a communication line, said apparatus comprising: A. receive logic for converting bit serial characters received from said line to bit parallel characters; B. transmit logic for converting bit parallel characters to bit serial characters for transfer over said lines; C. bit routing means included in both said receive logic and said transmit logic; D. a code unit coupled to receive bit parallel characters from said receive logic and from said transmit logic, said code unit comprising 1. means for detecting the identity of said characters; and 2. means for performing predetermined logic operations in response to the identity of certain ones of said characters; E. means for configuring said bit routing means included in said receive and transmit logic in order to adapt to a predetermined number of bits in said characters; F. means, included in the coupling between said code unit and said receive logic and said transmit logic, for enabling said code unit to be time shared between said receive logic and said transmit logic; and G. wherein said means for detecting comprises: 1. a comparator having first and second inputs; 2. means for selecting either said character from said receive logic or said character from said transmit logic for coupling to said first input; 3. means for providing a plurality of code characters; 4. means for sequentially selecting each of said plurality of code characters for coupling to said second input; and 5. means for indicating the identity of said characters provided by either said receive logic or said transmit logic when a positive comparison is made by said comparator.
Claim 3
Dependent Claim
23 words
means for selecting either said character from said receive logic or said character from said transmit logic for coupling to said first input;
Claim 4
Dependent Claim
23 words
means for selecting either said character from said receive logic or said character from said transmit logic for coupling to said first input;
Claim 5
Dependent Claim
88 words
means for performing predetermined logic operations in response to the identity of certain ones of said characters; E. means for configuring said bit routing means included in said receive and transmit logic in order to adapt to a predetermined number of bits in said characters; F. means, included in the coupling between said code unit and said receive logic and said transmit logic, for enabling said code unit to be time shared between said receive logic and said transmit logic; and G. wherein said means for detecting comprises:
Claim 6
Dependent Claim
88 words
means for performing predetermined logic operations in response to the identity of certain ones of said characters; E. means for configuring said bit routing means included in said receive and transmit logic in order to adapt to a predetermined number of bits in said characters; F. means, included in the coupling between said code unit and said receive logic and said transmit logic, for enabling said code unit to be time shared between said receive logic and said transmit logic; and G. wherein said means for detecting comprises:
Claim 7
Dependent Claim
139 words
Apparatus as in claim 1 wherein said means for indicating and said means for sequentially selecting comprise: A. counter means; B. means for enabling said counter means for counting when either said characters from said receive logic or said characters from said transmit logic are coupled to said first input; C. means for incrementing the count output of said counter means when said counter means is enabled for counting; D. a plurality of gate means each coupled to transfer one of said code characters to said second input in response to different counters as incremented from said counter means; and E. means for halting the incrementing of said counter means when said positive comparison is made, whereby the count of said counter means when halted indicates the identity of said character provided by either said receive or transmit logic.
Claim 8
Dependent Claim
8 words
means for providing a plurality of code characters;
Claim 9
Dependent Claim
8 words
means for providing a plurality of code characters;
Claim 10
Dependent Claim
91 words
Apparatus as in claim 2 wherein said receive logic and said transmit logic include clock means for enabling the transfer of said characters at a first frequency, and wherein said means for incrementing includes further clock means for incrementing said count at a second frequency, said second frequency greater than said first frequency, and said second frequency determined by the frequency of said first frequency, the time shared use of said code unit for both said receive logic and said transmit logic, and the number of said plurality of code characters.
Claim 11
Dependent Claim
49 words
Apparatus as in claim 1 wherein said means for performing predetermined logic operations comprises means for detecting the sequential occurrence of a first and a second character each identified by said means for indicating and means responsive to said sequential occurrence for enabling the operation of further logic means.
Claim 12
Dependent Claim
18 words
means for sequentially selecting each of said plurality of code characters for coupling to said second input; and
Claim 13
Dependent Claim
18 words
means for sequentially selecting each of said plurality of code characters for coupling to said second input; and
Claim 14
Dependent Claim
27 words
means for indicating the identity of said characters provided by either said receive logic or said transmit logic when a positive comparison is made by said comparator.
Claim 15
Dependent Claim
27 words
means for indicating the identity of said characters provided by either said receive logic or said transmit logic when a positive comparison is made by said comparator.
Claim 16
Dependent Claim
49 words
Apparatus as in claim 1 wherein said means for performing predetermined logic operations comprises: A. logic means for inhibiting the transfer of a first character identified by said means for indicating; and B. further logic means responsive to said first character for enabling the transfer of a second character.
Claim 17
Dependent Claim
39 words
Apparatus as in claim 5 wherein said first character and said second character are the same, whereIn said first character is a character utilized to provide synchronization of said apparatus, and wherein said second character is a data character.
Claim 18
Dependent Claim
59 words
Apparatus as in claim 1 wherein said means for performing predetermined logic operations comprises: A. logic means for inhibiting the transfer to said processor of synchronous characters identified by said means for indicating; and B. means for disabling said logic means for inhibiting when an apparent synchronous character is to be transferred to said processor as a data character.
Claim 19
Dependent Claim
89 words
Apparatus as in claim 1 wherein said means for configuring comprises at least one electromechanical connector having electrical terminals coupled so that one terminal is connected to one of at least two other terminals, said two other terminals coupled to respective inputs of said bit routing means and said respective inputs sensitive to the number of bits in a character, whereby said connection from said one terminal to one of said two other terminals enables the proper one of said respective inputs to be connected to said one terminal.
Claim 20
Dependent Claim
115 words
Apparatus as in claim 1 wherein each of said code characters is identified by a pattern of logic one''s and zero''s and wherein said means for providing a plurality of code characters comprises: A. a first portion of an electromechanical connector having terminals connected in circuit with said means for sequentially selecting; B. a second portion of said connector having terminals coupled for making electrical contact with said first portion; C. means for providing first and second potentials; and D. means for coupling said first and second potentials to said terminals of said second portion in an arrangement corresponding to the binary pattern of said logical one''s and zero''s of each of said code characters.
Claim 21
Dependent Claim
89 words
Apparatus as in claim 1 wherein said means for configuring comprises at least one electromechanical connector having electrical terminals coupled so that one terminal is connected to one of at least two other terminals, said two other terminals coupled to respective inputs of said bit routing means and said respective inputs sensitive to the number of bits in a character, whereby said connection from said one terminal to one of said two other terminals enables the proper one of said respective inputs to be connected to said one terminal.
Claim 22
Dependent Claim
131 words
Apparatus as in claim 1 wherein both said receive and transmit logic each include counters for maintaining synchronization of the number of bits in each of said characters, said counters being incremented from a reset condition a number of times corresponding to the number of bits in a character before being reset again, and wherein said means for configuring comprises at least one electromechanical connector having electrical terminals coupled so that for each of said counters one terminal is coupled to the reset input of the counter and at least two other terminals are respectively connected to those outputs of the counter which correspond to the number of bits of two different character lengths, and further comprising an electrical connection between said one terminal and one of said two other terminals.
Claim 23
Dependent Claim
135 words
Apparatus as in claim 1 wherein said receive logic comprises: A. a first shift register coupled to receive bits of said characters serially from said line; B. a second shift register coupled to receive bits of said characters after they have passed through said first shift register; C. means for comparing the contents of said first and second shift registers with a predetermined synchronization characters; D. means for establishing synchronization of said receive logic for further characters transferred over said line upon a positive comparison by said means for comparing; E. means for generating a control signal for each character received after said synchronization is established; and F. means for enabling the bits of said characterS in said first shift register to be transferred in parallel to said processor in response to said control signal.
Claim 24
Dependent Claim
86 words
Apparatus as in claim 12 further comprising: A. a buffer coupled between said first shift register and said processor so that said character is transferred to said buffer in response to said control signal; B. first means for indicating that said first shift register contains a full character; C. second means for indicating that said buffer contains a full character; and D. means for generating an overrun signal if both said first and second means for indicating indicate a full character when said signal is generated.
Claim 25
Dependent Claim
172 words
Apparatus as in claim 1 wherein said transmit logic comprises: A. a transmit buffer coupled for receiving bit parallel characters from said processor; B. a shift register coupled to receive a bit parallel character to be serially shifted by bit onto said line; C. control means coupled to provide said bit parallel character to said shift register, said control means having a plurality of inputs for receiving bit parallel characters from different sources; D. means for coupling one of said inputs to receive said bit parallel character from said transmit buffer; E. means for providing a plurality of code characters; F. means for coupling another of said inputs to receive one of said predetermined code characters; G. means included in said control means for inhibiting the normal transfer of bit parallel characters from said transmit buffer to said shift register in response to a control signal; and H. means included in said control means for enabling the transfer of said code characters to said shift register in response to said control signal.
Claim 26
Dependent Claim
115 words
Apparatus as in claim 14 wherein each of said code characters is identified by a pattern of logic one''s and zero''s and wherein said means for providing a plurality of code characters comprises: A. a first portion of an electromechanical connector having terminals connected in circuit with said means for sequentially selecting; B. a second portion of said connector having terminals coupled for making electrical contact with said first portion; C. means for providing first and second potentials; and D. means for coupling said first and second potentials to said terminals of said second portion in an arrangement corresponding to the binary pattern of said logical one''s and zero''s of each of said code characters.
Claim 27
Dependent Claim
68 words
Apparatus as in claim 14 further comprising: A. means for indicating that both said transmit buffer and said shift register do not include characters, said means for indicating generating an underrun signal in response to the lack of such characters; and B. means included in said control means for transferring synchronous characters over said line until a character from another source is ready for transfer over said line.
Claim 28
Dependent Claim
77 words
Apparatus as in claim 14 further comprising: A. a parity generator coupled to receive all bits of a character from said processor, said generator generating a parity bit in response to the state of the bits in said character; and B. means for providing said parity bit to the appropriate location in said buffer with said bits of said character, wherein said character to be transferred over said line via said shift register includes said parity bit.
Claim 29
Dependent Claim
125 words
Apparatus as in claim 17 further comprising: A. an electromechanical connector coupled to receive from said processor all bits of said character which are included in those character positions over the minimum character size; B. wherein said transmit buffer is coupled to receive directly from said processor only those bits of said character which are included in said minimum character size; C. means for providing said parity bit to said buffer by means of said connector; and D. means for providing circuits in said connector for said bits not included in said minimum character size and for said parity bit so that all bits of said character and said parity bit are provided to said transmit buffer in the designated location dependent on character length.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-27 | 1978-07-29 | 1979-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-27 | 1982-07-29 | 1983-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-27 | 1986-07-29 | 1987-01-28 | $7700.00 | Window Closed / Lapsed |