Synchronous communications adapter

Claim 1

A communications adapter for sending and/or receiving information in the form of a plurality of bits and generating multi-bit check characters with such sending or receiving, comprising: a shift register into and from which bits are serially shifted one at a time from loading and unloading ends of the register and into which and from which a plurality of bits are loaded and unloaded in parallel from loading and unloading sides of the register, first and second check character buffers each of which includes a plurality of bit positions, a data carry storage device holding the bits of said information that is sent or received, a check character carry storage device holding individual bits serially shifted out of said shift register, a first multi-line buffer-register path connecting said first check character buffer with said shift register for loading the bits contained in this buffer in parallel into said shift register, a first bit changing circuitry in one line of said path to have an input thereby from said first check character buffer and having a second input from said data carry storage device to have a bit therein applied to the bit changing circuitry so that the bit changing circuitry has a bit output for a combination of bits on its said inputs and applied through said line onto said shift register, a serial bit path connecting said unloading end of said shift register with said check character carry storage device and from thence extending to said loading end of said shift register so that a bit at said unloading end of the shift register may be serially shifted into said check character carry storage device so that a bit then in said check character carry storage device is serially shifted to the loading end of said shift register, a first multi-line register-buffer path connecting said shift register with said first check character buffer for unloading the bits in said shift register into said first character buffer in parallel after said serial shifting of the bits in said shift register has occurred, a second multi-line buffer-register path connecting said second character buffer with said shift register for loading the bits contained in this buffer in parallel into said shift register, a second bit changing circuitry in one line of said second buffer-register path to have an input thereby from said second check character buffer and having a second input from said check character carry storage device to have a bit therein applied to this bit changing circuitry so that this bit changing circuitry has a bit output for a combination of bits on its said inputs and applied through this line to said shift register, and a second multi-line register-buffer path connecting said shift register with said second check character buffer for unloading the bits in said shift register in parallel into said second check character buffer after a second serial shifting of the bits in said shift register has occurred subsequent to the loading of the contents of said second character buffer into said shift register, whereby multi-bit check characters are generated in said first and second check character buffers unique to the information that is sent and/or received as bits travel in said multi-line paths and bits are shifted serially in said shift register.