← Back to Patent Explorer
US4937575A Expired / Lapsed US ⏱️ 0.0 years remaining

Precision A/D converter utilizing a minimum of interface interconnections

Assignee: Honeywell Inc
•
Filing: 1988-10-18
•
Granted: 1990-06-26
•
Expires: 2008-10-18
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An A/D converter circuit generates a precise digital signal which accurately corresponds to an analog input signal. The A/D converter comprises a converter element, having a first and second, input terminal for receiving control signals, and having an output terminal, and further having at least one analog input terminal. The analog input signal is coupled to the analog input terminal, for converting the analog input signal to an uncorrected digital signal. The uncorrected digital signal includes inaccuracies of the parameter differentials of the converter element. A memory unit, stores information defining the actual parameter values of the converter element. A processor, controls the conversion of the analog input signal to the precise digital signal, wherein the actual parameter values are applied to the uncorrected digital signal thereby removing the inaccuracies of the converter element to obtain the precise digital signal.

Inventors

  • 👤 Karl T. Kummer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 22:10
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1009; H03M1/1033; H03M1/1038; H03M1/12; H03M1/1205; H03M1/122; H03M1/1225; H03M1/50; H03M1/52

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 320 words
An A/D converter, for generating a precise digital signal which accurately corresponds to an analog input signal, comprising: (a) integration circuit means, having at least one analog input terminal, the analog input signal being operatively coupled to the analog input terminal, for generating a count control signal, wherein the count control signal is at a first predetermined level and changes to a second predetermined level when conversion of the analog input signal to an uncorrected digital signal is completed, the point in time in which the change to said second predetermined level occurs from a predetermined point in time being proportional to the value of the analog input signal, the uncorrected digital signal including inaccuracies of parameter differentials of the A/D converter. (b) counter means, operatively connected to said integration circuit means, for counting a clocking signal, having a predetermined frequency, from the predetermined point in time to the point in time in which the count control signal changes to the second predetermined level, the counter means containing the uncorrected digital signal upon completion of the count; (c) controller means, having a first and second input terminal for receiving first and second control signals, and having an output terminal, for controlling the integration circuit means in response to the control signals; (d) memory means, operatively connected to the controller means and to the integration circuit means, for storing information defining the actual parameter values of the A/D converter; and (e) processor means, operatively connected to the first and second input terminal of said controller means for coupling a first and second control signal to said controller means, and further operatively connected to the output terminal of said controller means, for controlling the conversion of said analog input signal to said precise digital signal, wherein said actual parameter values are applied to the uncorrected digital signal thereby removing the inaccuracies of the A/D converter means to obtain said precise digital signal.
Claim 2
Dependent Claim 320 words
An A/D converter, for generating a precise digital signal which accurately corresponds to an analog input signal, comprising: (a) integration circuit means, having at least one analog input terminal, the analog input signal being operatively coupled to the analog input terminal, for generating a count control signal, wherein the count control signal is at a first predetermined level and changes to a second predetermined level when conversion of the analog input signal to an uncorrected digital signal is completed, the point in time in which the change to said second predetermined level occurs from a predetermined point in time being proportional to the value of the analog input signal, the uncorrected digital signal including inaccuracies of parameter differentials of the A/D converter. (b) counter means, operatively connected to said integration circuit means, for counting a clocking signal, having a predetermined frequency, from the predetermined point in time to the point in time in which the count control signal changes to the second predetermined level, the counter means containing the uncorrected digital signal upon completion of the count; (c) controller means, having a first and second input terminal for receiving first and second control signals, and having an output terminal, for controlling the integration circuit means in response to the control signals; (d) memory means, operatively connected to the controller means and to the integration circuit means, for storing information defining the actual parameter values of the A/D converter; and (e) processor means, operatively connected to the first and second input terminal of said controller means for coupling a first and second control signal to said controller means, and further operatively connected to the output terminal of said controller means, for controlling the conversion of said analog input signal to said precise digital signal, wherein said actual parameter values are applied to the uncorrected digital signal thereby removing the inaccuracies of the A/D converter means to obtain said precise digital signal.
Claim 3
Dependent Claim 110 words
An A/D converter, for generating a precise digital signal according to claim 1, wherein said memory means: is operatively connected to said first and second input terminal of said controller converter means and wherein said memory means comprises a memory having an input terminal and an output terminal, information transfers between said memory means and said processor means being serial information transfers according to a predetermined protocol, said first and second terminals of the controller converter means being the same terminals utilized as connection points for the transfer of information between said controller converter means and said processor means, thereby minimizing the number of interface connections of said A/D converter.
Claim 4
Dependent Claim 34 words
An A/D converter, for generating a precise digital signal according to claim 2, wherein the A/D converter parameter values stored in said memory means include the actual parameter values of the integration circuit means.
Claim 5
Dependent Claim 25 words
An A/D converter, for generating a precise digital signal according to claim 1, wherein said memory means is semi-permanently associated with said integration circuit means.

References Cited (Backward Citations)

US4151518A Cited
US4149256A Cited
US4141065A Cited
US4425561A Cited
US4309767A Cited
US4510569A Cited
US4567466A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-06-25 1993-12-25 1994-06-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-06-25 1997-12-25 1998-06-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-06-25 2001-12-25 2002-06-26 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag