Self-characterizing analog-to-digital converter

Claim 1

An A/D converter architecture including an A/D converter and digital logic circuitry on a common chip, said A/D converter having an analog signal input for receiving a cyclically recurring test signal waveform and a digital code output, said digital logic circuitry comprising: means for dividing the output signal of said A/D converter into a plurality of bins including bin counter means responsive to a next bin count input signal for providing a bin count output signal corresponding to a specific selectable digital value expected in said digital output code; comparator means coupled to said A/D converter and responsive to said signal produced at the digital code output of said A/D converter and to said bin count output signal for generating an output signal for each match of said digital code output signal and said bin count output signal over a predetermined multiplicity of test signal waveform cycles; and histogram counter means reset by said next bin count input signal and incremented by said output signal of said comparator means for accumulating code-density data, whereby to generate a histogram of digital codes correlated with said bins, said histogram being readable at a lower rate than a conversion rate of said A/D converter to provide dynamic characterization of said A/D converter.