Decompaction of stored data in automatic test systems

Claim 2

In test equipment for testing a unit under test, decompaction apparatus for decoding N bit parallel binary data words including binary data which is compacted and providing uncompacted serial binary data therefrom to an input of the unit under test, the parallel binary data words including a code identifier field, the decompaction apparatus comprising: memory means for storing N bit parallel binary data words; a first decoder coupled to receive at least part of an N bit parallel binary data word read from the memory means and selectively capable of being enabled to output alone or with the memory means uncompacted parallel binary data; a second decoder coupled to receive at least part of an N bit parallel binary data word read from the memory means and selectively capable of being enabled to output alone or with the memory means uncompacted parallel binary data; the uncompacted binary data associated with at least one of the first and second decoders having a greater number of bits than the parallel data stored in the memory means; decoding means for receiving the code identifier field of an N bit parallel binary data word read from the memory means, decoding it and causing the decoder specified by the code identifier field to be enabled; a multiplexer coupled at least to the first and second decoders to receive parallel uncompacted data associated with the first and second decoders and selectively output received parallel data associated with one of the decoders at a time; output means coupled to the multiplexer for receiving parallel uncompacted data therefrom and providing serial uncompacted data to an output of the decompaction apparatus for supply to the input of the unit under test; and control means for controlling reading of data from the memory means and operation of the decoding means, the decoders, the multiplexer and the output means.

Claim 3

In the test equipment according to claim 1 wherein the multiplexer comprises first and second multiplexers and the output means comprises first and second shift registers, the first multiplexer selectively coupling data associated with the first and second decoders to the first shift register and the second multiplexer selectively coupling data associated with the first and second decoders to the second shift register, the control means alternately causing the first multiplexer to supply uncompacted parallel data associated with one of the first and second decoders to the first shift register and the second multiplexer to supply uncompacted parallel data associated with said one decoder to the second shift register, and alternately causing uncompacted data to be serially shifted to the apparatus output from the shift register that is not receiving data from the first and second multiplexers.

Claim 4

The apparatus according to claim 1 wherein the memory means includes an addressable memory for storing the N bit data words and means coupled to the memory means for storing an N bit data word read from the memory.

Claim 5

The apparatus according to claim 1 wherein at least one of the first and second decoder means in response to an N bit word stored in the memory means provides parallel data having more than N bits to the multiplexer.

Claim 6

The apparatus according to claim 4 wherein the memory means includes a readable memory for storing a plurality of N bit parallel words and means for storing an N bit parallel word read from the memory, and wherein the control means causes N bit words to be read from the memory to the storing means at a given rate and causes serial data to be output by the output means such that the rate at which serial data is output is faster than the given rate at which data is received in the storing means.

Claim 7

In the test equipment according to claim 1 wherein the output means comprises output storage means coupled to the multiplexer for temporarily storing uncompacted parallel data associated with the first and second decoders, the control means causing the storage means to serially output the uncompacted data stored therein.

Claim 8

In the test equipment according to claim 6 including a third decoder for causing in cooperation with the control means uncompacted parallel data to be generated by at least one of the first and second decoders based on at least one data field in the parallel data word supplied to the third decoder.

Claim 9

In the test equipment according to claim 6 wherein the second decoder comprises means for generating when the second decoder is enabled uncompacted binary data of all ones, all zeros or alternating ones and zeros of a selectable length from data contained in a parallel data word.

Claim 10

In the test equipment according to claim 6 wherein the first decoder includes means receiving a first part of the data in the parallel data word, and wherein the memory means is coupled to supply a second part of the data in the parallel data word to the multiplexer, the control means causing the multiplexer to couple the second part of the data to the apparatus output when the first decoder is enabled.

Claim 11

In the test equipment according to claim 9 wherein the first decoder when enabled causes uncompacted data to be coupled to the multiplexer in response to the first part of the parallel data word.

Claim 12

In the test equipment according to claim 6 wherein the second decoder comprises means for generating when the second decoder is enabled uncompacted binary data consisting of at least one fixed pattern of ones and zeros from the data contained in a parallel data word.

Claim 13

In the test epuipment according to claim 11 wherein the second decoder includes means for repeating the fixed pattern a number of times specified in a data field of the parallel data word.

Claim 14

In automatic test epuipment including a memory configured to store parallel data, and means for accessing parallel data from the memory and supplying data to a unit under test, a decompaction apparatus for decoding parallel binary data stored in the memory and providing uncompacted serial binary data to the unit under test, the parallel binary data including binary data which is compacted and compaction codes, the decompaction apparatus comprising: means for storing parallel data read from the memory; a first decoder coupled to receive at least part of the parallel binary data in the storing means and selectively enablable to output alone or with the storing means uncompacted parallel binary data; a second decoder coupled to receive at least part of the parallel binary data in the storing means and selectively enablable to output alone or with the storing means uncompacted parallel binary data; the uncompacted binary data associated with at least one of the first and second decoders having a greater number of bits than the parallel data stored in the storing means; decoding means for receiving the compaction code of parallel binary data in the storing means, decoding it and causing the decoder specified by the compaction code to be enabled; a multiplexer coupled at least to the first and second decoders to receive parallel uncompacted data associated with the first and second decoders and selectively output the parallel data associated with one of the decoders at a time; output means coupled to the multiplexer for receiving parallel uncompacted data therefrom and providing serial uncompacted data on at least one output pin of the apparatus for transmission to the unit under test; and control means for controlling reading of parallel data from the memory to the storing means and operation of the decoding means the decoders, the multiplexer and the output means.

Claim 15

In automatic test epuipment including a memory configured to store parallel data, and means for accessing parallel data from the memory and supplying data to a unit under test, a decompaction apparatus for decoding parallel binary data stored in the memory and providing uncompacted serial binary data to the unit under test, the parallel binary data including binary data which is compacted and compaction codes, the decompaction apparatus comprising: means for storing parallel data read from the memory; a first decoder coupled to receive at least part of the parallel binary data in the storing means and selectively enablable to output alone or with the storing means uncompacted parallel binary data; a second decoder coupled to receive at least part of the parallel binary data in the storing means and selectively enablable to output alone or with the storing means uncompacted parallel binary data; the uncompacted binary data associated with at least one of the first and second decoders having a greater number of bits than the parallel data stored in the storing means; decoding means for receiving the compaction code of parallel binary data in the storing means, decoding it and causing the decoder specified by the compaction code to be enabled; a multiplexer coupled at least to the first and second decoders to receive parallel uncompacted data associated with the first and second decoders and selectively output the parallel data associated with one of the decoders at a time; output means coupled to the multiplexer for receiving parallel uncompacted data therefrom and providing serial uncompacted data on at least one output pin of the apparatus for transmission to the unit under test; and control means for controlling reading of parallel data from the memory to the storing means and operation of the decoding means the decoders, the multiplexer and the output means.

Claim 16

In the automatic test equipment according to claim 13, wherein at least one of the first and second decoders of the decompaction apparatus in response to an N bit parallel word stored in the storing means provides parallel data having more than N bits to the multiplexer.

Claim 17

In the automatic test equipment according to claim 13, wherein the control means causes N bit parallel data words to be read from the memory to the storing means at a given rate and causes serial data to be output by the output means such that the rate at which serial data is output is faster than the given rate at which data is received in the storing means.

Claim 18

In the automatic test equipment according to claim 13, wherein the output means comprises output storage means coupled to the multiplexer for temporarily storing uncompacted parallel data associated with the first and second decoders, the control means causing the storage means to serially output the uncompacted data stored therein.

Claim 19

In the automatic test equipment according to claim 13, wherein the multiplexer comprises first and second multiplexers and the output means comprises first and second shift registers, the first multiplexer selectively coupling data associated with the first and second decoders to the first shift register and the second multiplexer selectively coupling data associated with the first and second decoders to the second shift register, the control means alternately causing the first multiplexer to supply uncompacted parallel data associated with one of the first and second decoders to the first shift register and the second multiplexer to supply uncompacted parallel data associated with said one decoder to the second shift register, and alternately causing uncompacted data to be serially shifted to the apparatus output from the shift register that is not receiving data from the first and second multiplexers.

Claim 20

In the automatic test equipment according to claim 13, wherein the second decoder comprises means for generating when the second decoder is enabled uncompacted binary data of all ones, all zeros or alternating ones and zeros of a selectable length from data contained in parallel data stored in the storing means.

Claim 21

In the automatic test equipment according to claim 13, wherein the second decoder comprises means for generating when the second decoder is enabled uncompacted binary data consisting of at least one fixed pattern of ones and zeros from data contained in parallel data stored in the storing means.

Claim 22

In the automatic test equipment according to claim 13, wherein the second decoder includes means for repeating the fixed pattern a number of times specified in a data field of parallel data stored in the storing means.

Claim 23

In the automatic test equipment according to claim 13, including a third decoder for causing in cooperation with the control means uncompacted parallel data to be generated by at least one of the first and second decoders based on at least one data field in the parallel data supplied to the third decoder.

Claim 24

In the automatic test equipment according to claim 13, wherein the first decoder includes means receiving a first part of the data in the parallel data stored in the storing means, and wherein the storing means is coupled to supply a second part of the data in the parallel data stored in the storing means to the multiplexer, the control means causing the multiplexer to couple the second part of the data to the apparatus output when the first decoder is enabled.

Claim 25

In the automatic test equipment according to claim 22, wherein the first decoder when enabled causes uncompacted data to be coupled to the multiplexer in response to the first part of the parallel data stored in the storing means.

Claim 26

In test equipment for testing a unit under test, decompaction apparatus for decoding parallel binary data including compaction codes and binary data which is compacted and providing uncompacted serial binary data therefrom to an input of the unit under test, the decompaction apparatus comprising: memory means for storing the parallel binary data; first selectively capable of being enabled decoder means for decoding parallel binary data from the data stored in the memory means and providing alone or with the memory means uncompacted binary data; second selectively enable decoder means for decoding parallel binary data from the data stored in the memory means and providing alone or with the memory means uncompacted binary data; the uncompacted binary data associated with at least one of the first and second decoder means having a greater number of bits than the parallel data stored in the memory means; decoding means for decoding compaction codes and selectively causing at least one of the first and second decoder means to be enabled in accordance therewith; output means coupled to receive uncompacted binary data associated with the first and second decoder means and to output uncompacted serial binary data on an output of the decompaction apparatus for supply to the input of the unit under test; and control means for controlling reading of parallel binary data from the memory means and operation of the decoder means, the decoding means and the output means.

Claim 27

In test equipment for testing a unit under test, decompaction apparatus for decoding parallel binary data including compaction codes and binary data which is compacted and providing uncompacted serial binary data therefrom to an input of the unit under test, the decompaction apparatus comprising: memory means for storing the parallel binary data; first selectively capable of being enabled decoder means for decoding parallel binary data from the data stored in the memory means and providing alone or with the memory means uncompacted binary data; second selectively enable decoder means for decoding parallel binary data from the data stored in the memory means and providing alone or with the memory means uncompacted binary data; the uncompacted binary data associated with at least one of the first and second decoder means having a greater number of bits than the parallel data stored in the memory means; decoding means for decoding compaction codes and selectively causing at least one of the first and second decoder means to be enabled in accordance therewith; output means coupled to receive uncompacted binary data associated with the first and second decoder means and to output uncompacted serial binary data on an output of the decompaction apparatus for supply to the input of the unit under test; and control means for controlling reading of parallel binary data from the memory means and operation of the decoder means, the decoding means and the output means.

Claim 28

In the test equipment according to claim 22 wherein the output means comprises means for temporarily storing the uncompacted data it receives.

Claim 29

In the test equipment according to claim 24 including first and second multiplexer means coupled at least to the first and second decoder means and to the output means, and wherein the output means comprises first and second output storage means, the first multiplexer means selectively supplying parallel uncompacted data associated with the first and second decoder means to the first output storage means and the second multiplexer means selectively supplying parallel uncompacted data associated with the first and second decoder means to the second output storage means, the first and second output storage means temporarily storing parallel uncompacted data therein, the control means alternately causing the first multiplexer means to supply the data associated with one of the first and second decoder means to the first output storage means and the second multiplexer means to supply the data associated with said one decoder means to the second output storage means, and to alternately cause the data stored in the first and second output storage means that is not receiving data from the first and second multiplexer means to be serially outputted on the decompaction apparatus output.

Claim 30

In the test equipment according to claim 24 including third decoder means for causing in cooperation with the control means uncompacted data to be generated by at least one of the first and second decoder means based on data in the parallel data supplied to the third decoder means.

Claim 31

In the test equipment according to claim 24 wherein the memory means includes an addressable memory for storing N bit data words and means coupled to the memory means for storing an N bit data word read from the memory.

Claim 32

In the test equipment according to claim 24 wherein at least one of the first decoder means and the memory means provides uncompacted parallel data to the output means when the first decoder means is enabled, and wherein the second decoder means provides uncompacted parallel data to the output means when the second decoder means is enabled, the control means causing the parallel uncompacted data to be supplied to the output means and the output means to serially output the uncompacted data on the decompaction apparatus output.

Claim 33

In the test equipment according to claim 24 wherein the memory means includes means for storing N bit parallel data, the apparatus including means for supplying N bit parallel data to the storing means at a given rate, wherein the control means causes serial data to be output by the output means such that the rate at which serial data is output is faster than the given rate at which N bit parallel data is received in the storing means.

Claim 34

In the test equipment according to claim 30 wherein the second decoder means comprises means for generating from the parallel data uncompacted binary data of all ones, all zeros or alternating ones and zeros of a selectable length exceeding the length of the parallel data stored in the storing means.

Claim 35

In the test equipment according to claim 30 wherein the first decoder means includes means receiving a first part of the data in the parallel data, and wherein the memory means is coupled to the output means and supplies a second part of the data in the parallel data thereto, the control means causing the output means to couple the second part of the data to the decompaction apparatus output when the first decoder means is selectively enabled.

Claim 36

In the test equipment according to claim 32 wherein the first decoder means when enabled causes uncompacted data to be coupled to the output means in response to the first part of the data.

Claim 37

In the test equipment according to claim 30 wherein the second decoder means comprises means for generating from the parallel data uncompacted binary data consisting of at least one fixed pattern of ones and zeros exceeding the length of the parallel data stored in the storing means.

Claim 38

In the test equipment according to claim 34 wherein the second decoder means includes means for repeating the fixed pattern a number of times in accordance with data contained in the parallel data supplied to the second decoder means.