US5383269A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making three dimensional integrated circuit interconnect module
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-09-02
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Granted: 1995-01-24
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Expires: 2013-09-02
Abstract
Abstract A three dimensional integrated circuit interconnect for connecting a plurality of chips in a module with a standard footprint for pin grid array or quad flat pack mounting. Each IC is mounted on a custom interconnect slice and tested. The slices are stacked together with electrical connections from one slice layer to the next. The module may use multi-layer ceramic slices or printed circuit board materials.
Inventors
- 👤 Claude Rathmell
- 👤 Carroll S. Vance
- 👤 David W. Barnes
- 👤 Seyed H. Hashemi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:17
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/36; H10; H10W; H10W90/00; H10W90/701; H10W90/721; H10W90/722; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/49169; Y10T29/49171; Y10T29/49172
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
114 words
A method of making a three-dimensional IC interconnect module comprising, making a plurality of slices having at least one integrated circuit having a plurality of input/output pads and a lead interconnect electrically connected to each pad, said lead interconnects terminating at various locations within the periphery of the slices and surrounding the integrated circuits, testing each slice individually to test the integrated circuits and the lead interconnects, stacking said slices together and aligning a plurality of signal connections extending transversely through the plurality of slices within the periphery of the slices and surrounding the integrated circuits, electrically connecting the lead interconnects to the signal connections, and testing the stacked slices through the signal connections.
Claim 2
Independent Claim
114 words
A method of making a three-dimensional IC interconnect module comprising, making a plurality of slices having at least one integrated circuit having a plurality of input/output pads and a lead interconnect electrically connected to each pad, said lead interconnects terminating at various locations within the periphery of the slices and surrounding the integrated circuits, testing each slice individually to test the integrated circuits and the lead interconnects, stacking said slices together and aligning a plurality of signal connections extending transversely through the plurality of slices within the periphery of the slices and surrounding the integrated circuits, electrically connecting the lead interconnects to the signal connections, and testing the stacked slices through the signal connections.
Claim 3
Dependent Claim
47 words
The method of claim 1 including, providing a plurality of openings in each slice, one of said openings positioned adjacent the termination of each lead interconnect, providing a plurality of parallel extending signal connection pins, and stacking said slices together by inserting said openings over the pins.
Claim 4
Dependent Claim
25 words
The method of claim 2 including, electrically connecting the lead interconnects to the pins by heating the pins and soldering the interconnects and pins together.
Claim 5
Dependent Claim
20 words
The method of claim 1 including the step of testing each slice individually by first testing only the lead interconnects.
Claim 6
Dependent Claim
45 words
The method of claim 1 including providing a plurality of solder filled openings in each slice, one of said openings positioned adjacent the termination of each lead interconnect, and heating the stacked together slices for connecting the solder filled openings together forming the signal connections.
Claim 7
Dependent Claim
26 words
The method of claim 1 wherein the slices are ceramic and said lead interconnects are formed by placing a film of interconnect circuitry between ceramic slices.
Claim 8
Dependent Claim
60 words
The method of claim 1 wherein the slices are formed by assembling a bottom metallic layer, a middle layer having an integrated circuit having a plurality of input/output pads and having a lead interconnect electrically connected to each pad, and a top encapsulation layer, and providing openings in all of said layers within their periphery and surrounding the integrated circuits.
Claim 9
Dependent Claim
44 words
The method of claim 1 wherein the integrated circuits have input protection diodes at each pad, and the testing includes, applying a negative voltage to each of the lead interconnects when testing each slice, and measuring the current drawn for each of the interconnects.
Claim 10
Dependent Claim
61 words
The method of claim 1 wherein the slices are formed by assembling a bottom heat sink layer, a middle layer having an integrated circuit having a plurality of input/output pads and having a lead interconnect electrically connected to each pad, and a top insulation layer, and providing openings in all of said layers within their periphery and surrounding the integrated circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-23 | 2002-07-25 | 2003-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-23 | 2006-07-25 | 2007-01-24 | $7700.00 | Window Closed / Lapsed |