US5364816A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabrication method for III-V heterostructure field-effect transistors
Assignee: United States Department of the Navy
•
Filing: 1993-01-29
•
Granted: 1994-11-15
•
Expires: 2013-01-29
Abstract
Abstract A heterojunction device, and a method for producing the device. A gate air bridge is formed at the mesa sidewall between the active region and the gate bonding pad to lower the gate leakage current. The device has a double recessed gate to reduce local fields in the vicinity of the gate. The fabrication method uses dielectric intermediate and final passivation layers to optimize the double-recess profile and control the extension of the high-field region between the gate and the drain. This combination increases the breakdown potential of the device, but minimizes the effective gate length of the device, preserving high frequency performance.
Inventors
- 👤 J. Brad Boos
- 👤 Walter Kruppa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:52
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/015; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/4732; H10D30/4735; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
313 words
A method of fabricating a heterojunction semiconductor device which includes a source, drain, gate and a channel, said method comprising the steps of: epitaxially growing a sample with a heterojunction, said heterojunction having a first and a second layer of semiconductor material, said first layer being of a smaller bandgap material that of said second layer; forming a third layer of semiconductor material on said second layer; forming source and drain metalizations on top of said third layer; growing a first insulating layer on of said metalizations; applying a photoresist layer atop said first insulating layer and delineating a gate opening in said photoresist above said first insulating layer; using said opening as a mask for forming a corresponding gate recess in said first insulating layer; forming a gate recess in said third layer; a first widening step, said first widening step being effective to cause said gate opening to be preferentially widened with respect to said gate recess in said third layer in a direction generally parallel to said third layer to increase the width of said gate opening in said first insulating layer; a second step for widening, said second stop for widening being effective to form a gate recess of a first width in said second layer, and a gate recess of a second width in said third layer, said second width being larger than said first width; providing gate metalization, said gate metalization comprising a gate stripe and a gate bonding pad, said stripe being disposed in said gate recess in said second layer; growing a second insulating layer on said source, drain and gate metalizations; applying a photoresist layer atop said second insulating layer and delineating a mesa photoresist opening above said second insulating layer; and forming a mesa through each of said layers effective to dispose an air-gap in said layers between said stripe and said pad.
Claim 2
Independent Claim
313 words
A method of fabricating a heterojunction semiconductor device which includes a source, drain, gate and a channel, said method comprising the steps of: epitaxially growing a sample with a heterojunction, said heterojunction having a first and a second layer of semiconductor material, said first layer being of a smaller bandgap material that of said second layer; forming a third layer of semiconductor material on said second layer; forming source and drain metalizations on top of said third layer; growing a first insulating layer on of said metalizations; applying a photoresist layer atop said first insulating layer and delineating a gate opening in said photoresist above said first insulating layer; using said opening as a mask for forming a corresponding gate recess in said first insulating layer; forming a gate recess in said third layer; a first widening step, said first widening step being effective to cause said gate opening to be preferentially widened with respect to said gate recess in said third layer in a direction generally parallel to said third layer to increase the width of said gate opening in said first insulating layer; a second step for widening, said second stop for widening being effective to form a gate recess of a first width in said second layer, and a gate recess of a second width in said third layer, said second width being larger than said first width; providing gate metalization, said gate metalization comprising a gate stripe and a gate bonding pad, said stripe being disposed in said gate recess in said second layer; growing a second insulating layer on said source, drain and gate metalizations; applying a photoresist layer atop said second insulating layer and delineating a mesa photoresist opening above said second insulating layer; and forming a mesa through each of said layers effective to dispose an air-gap in said layers between said stripe and said pad.
Claim 3
Dependent Claim
40 words
The method of claim 1 wherein the heterojunction region of said layered sample includes an epitaxially grown undoped layer as the narrow bandgap layer and epitaxially grown doped layer as the wide bandgap material, whereby a HEMT device is produced.
Claim 4
Dependent Claim
40 words
The method of claim 1 wherein the heterojunction region of said layered sample includes an epitaxially grown doped layer as the narrow bandgap layer and epitaxially grown undoped layer as the wide bandgap material, whereby a HFET device is produced.
Claim 5
Dependent Claim
31 words
The method of claim 1 wherein the said layered sample includes the same material for the narrow bandgap layer as for the wide bandgap material, whereby a FET device is produced.
Claim 6
Dependent Claim
22 words
The method of claim 1 wherein the epitaxially grown narrow bandgap layer is InGaAs and epitaxially grown wide bandgap material is InAlAs.
Claim 7
Dependent Claim
19 words
The method of claim 1 wherein said first and said second insulating layers are Si 3 N 4 .
Claim 8
Dependent Claim
26 words
The method of claim 6 wherein said forming of said corresponding gate recess in said first insulating layer is done by CF 4 reactive ion etching.
Claim 9
Dependent Claim
25 words
The method of claim 1 wherein said second widening step is done by H 3 PO 4 :H 2 O 2 :H 2 O etching.
Claim 10
Dependent Claim
19 words
The method of claim 6 wherein said first widening step is done by SiF 4 :2%O 2 plasma etching.
Claim 11
Dependent Claim
27 words
The method of claim 1 wherein said step of forming a mesa is done by H 3 PO 4 :H 2 O 2 :H 2 O etching.
Claim 12
Independent Claim
346 words
A method of fabricating a heterojunction semiconductor device which includes a source, drain, gate and a channel, said method comprising the steps of: epitaxially growing a sample with a heterojunction, said heterojunction having a first and a second layer of semiconductor material said first layer being of a smaller bandgap material than that of said second layer; forming a third layer of semiconductor material on said second layer; forming source and drain metalizations on top of said third layer; growing a first insulating layer on said layer and said metalizations; applying a photoresist layer atop said first insulating layer and delineating a gate opening in said photoresist above said first insulating layer; using said opening as a mask for forming a corresponding gate recess in said first insulating layer; forming a gate recess in said third layer; a first widening step, said first widening step being effective to cause said gate opening to be preferentially widened with respect to said gate recess in said third layer in a direction generally parallel to said third layer to increase the width of said gate opening in said first insulating layer; a second widening step, said second widening step being effective to form a gate recess of a first width in said second layer, and a gate recess of a second width in said third layer, said second width being larger than said first width and larger than said gate recess in said insulating layer, wherein said insulating layer is undercut by said gate recess of said second width; providing gate metalization, said gate metalization comprising a gate stripe and a gate bonding pad, said stripe being disposed in said gate recess in said second layer; following said step for providing gate metalization, growing a second insulating layer on of said source, drain and gate metalizations; applying a photoresist layer atop said second insulating layer and delineating a mesa photoresist opening above said second insulating layer; and forming a mesa through each of said layers effective to dispose an air-gap in said layers between said stripe and said pad.
Claim 13
Independent Claim
346 words
A method of fabricating a heterojunction semiconductor device which includes a source, drain, gate and a channel, said method comprising the steps of: epitaxially growing a sample with a heterojunction, said heterojunction having a first and a second layer of semiconductor material said first layer being of a smaller bandgap material than that of said second layer; forming a third layer of semiconductor material on said second layer; forming source and drain metalizations on top of said third layer; growing a first insulating layer on said layer and said metalizations; applying a photoresist layer atop said first insulating layer and delineating a gate opening in said photoresist above said first insulating layer; using said opening as a mask for forming a corresponding gate recess in said first insulating layer; forming a gate recess in said third layer; a first widening step, said first widening step being effective to cause said gate opening to be preferentially widened with respect to said gate recess in said third layer in a direction generally parallel to said third layer to increase the width of said gate opening in said first insulating layer; a second widening step, said second widening step being effective to form a gate recess of a first width in said second layer, and a gate recess of a second width in said third layer, said second width being larger than said first width and larger than said gate recess in said insulating layer, wherein said insulating layer is undercut by said gate recess of said second width; providing gate metalization, said gate metalization comprising a gate stripe and a gate bonding pad, said stripe being disposed in said gate recess in said second layer; following said step for providing gate metalization, growing a second insulating layer on of said source, drain and gate metalizations; applying a photoresist layer atop said second insulating layer and delineating a mesa photoresist opening above said second insulating layer; and forming a mesa through each of said layers effective to dispose an air-gap in said layers between said stripe and said pad.
References Cited (Backward Citations)
US4289846A
Cited
US4860068A
Cited
US4578127A
Cited
US4624740A
Cited
JPS6242424A
Cited
US4981808A
Cited
US5084744A
Cited
US4769683A
Cited
US5079620A
Cited
US5091759A
Cited
US5087950A
Cited
US5084743A
Cited
JPH0471691A
Cited
US5081511A
Cited
US5060031A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-14 | 1998-05-16 | 1998-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-14 | 2002-05-16 | 2002-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-14 | 2006-05-16 | 2006-11-15 | $7700.00 | Window Closed / Lapsed |