US4769683A
Expired / Lapsed
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Superlattice gate field effect transistor
Assignee: NXP USA Inc
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Filing: 1987-06-22
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Granted: 1988-09-06
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Expires: 2007-06-22
Abstract
Abstract A quasi 1-dimensional electron gas transistor has been provided having a source electrode and a drain electrode. A plurality of electrodes are positioned between the source and drain electrodes in a manner which are parallel to the electron flow between the source and the drain electrodes. In one embodiment, the electrodes are interconnected by a gate electrode while in an alternate embodiment all the electrodes are connected to the source electrode and insulated from the gate electrode. This device provides a quantum wire for quasi 1-dimensional electron flow.
Inventors
- 👤 Herbert Goronkin
- 👤 George N. Maracas
- 👤 Richard Nguyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 04:30
CPC Classifications
B; B82; B82Y; B82Y10/00; H; H10; H10D; H10D30/00; H10D30/40; H10D30/43; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
46 words
A superlattice gate field effect transistor comprising: a source; a drain; and a plurality of 1-dimensional channel guide electrodes arranged in a parallel configuration between the source and drain, wherein any electron flow between the source and drain is parallel to the 1-dimensional channel guide electrodes.
Claim 2
Dependent Claim
46 words
A superlattice gate field effect transistor comprising: a source; a drain; and a plurality of 1-dimensional channel guide electrodes arranged in a parallel configuration between the source and drain, wherein any electron flow between the source and drain is parallel to the 1-dimensional channel guide electrodes.
Claim 3
Dependent Claim
24 words
The superlattice gate field effect transistor of claim 1 wherein the plurality of 1-dimensional channel guide electrodes are all interconnected by a transverse member.
Claim 4
Dependent Claim
53 words
The superlattice gate field effect transistor of claim 1 wherein the plurality of 1-dimensional channel guide electrodes are all connected to the source, and further including a single gate electrode positioned over and insulated from the plurality of 1-dimensional channel guide electrodes and being transverse to the plurality of 1-dimensional channel guide electrodes.
Claim 5
Dependent Claim
57 words
A superlattice gate III-V compound field effect transistor comprising a source electrode; a drain electrode; and a plurality of electrodes positioned between the source and the drain wherein a first end of each of the plurality of electrodes is near the source and a second end of each of the plurality of electrodes is near the drain.
Claim 6
Dependent Claim
57 words
A superlattice gate III-V compound field effect transistor comprising a source electrode; a drain electrode; and a plurality of electrodes positioned between the source and the drain wherein a first end of each of the plurality of electrodes is near the source and a second end of each of the plurality of electrodes is near the drain.
Claim 7
Dependent Claim
27 words
The superlattice gate III-V compound field effect transistor of claim 4 further including a connecting member to interconnect the plurality of electrodes to form a gate electrode.
Claim 8
Dependent Claim
44 words
The superlattice gate III-V compound field effect transistor of claim 4 wherein the plurality of electrodes all have their first end connected to the source, and further including a member transverse to and isolated from the plurality of electrodes to form a gate electrode.
Claim 9
Dependent Claim
67 words
A superlattice gate field effect transistor comprising a source electrode; a drain electrode; and a plurality of electrodes located between the source electrode and the drain electrode to form the superlattice gate, wherein 1-dimensional electron channel is formed between the plurality of electrodes during operation of the field effect transistor so electrons can flow between the source electrode and the drain electrode in the 1-dimensional electron channel.
Claim 10
Dependent Claim
67 words
A superlattice gate field effect transistor comprising a source electrode; a drain electrode; and a plurality of electrodes located between the source electrode and the drain electrode to form the superlattice gate, wherein 1-dimensional electron channel is formed between the plurality of electrodes during operation of the field effect transistor so electrons can flow between the source electrode and the drain electrode in the 1-dimensional electron channel.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-09-06 | 1992-03-07 | 1992-09-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-09-06 | 1996-03-07 | 1996-09-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-09-06 | 2000-03-07 | 2000-09-06 | $7700.00 | Window Closed / Lapsed |