US5060031A — Complementary heterojunction field effect transis…

Claim 1

Independent Claim 334 words

A complementary GaAs based heterostructure integrated circuit structure comprising: a semi-insulating GaAs substrate having a major surface; a first epitaxial layer of substantially intrinsic GaAs grown directly over the major surface; a second epitaxially grown layer of substantially intrinsic AlGaAs grown directly over the first layer; a third epitaxially grown layer of substantially intrinsic GaAs grown over the second layer; a fourth epitaxial layer of substantially intrinsic InGaAs grown over the third layer; a fifth epitaxial layer of substantially intrinsic AlAs grown over the fourth layer; a sixth layer of substantially intrinsic AlGaAs grown over the fifth layer; first and second N-type regions formed in the surface of the sixth layer and extending to the third layer, wherein a portion of the fourth layer which lies between the first and second N-type regions forms a channel of an N-channel HFET; a conductive material formed on top of the sixth layer between and separated from the first and second N-type regions and making a rectifying contact with the sixth layer, wherein the conductive material serves as a gate electrode of the N-channel HFET; electrodes formed on the first and second N-type regions to serve as source-drain electrodes of the N-channel HFET; first and second P-type regions formed in the surface of the sixth layer and extending to the third layer, wherein a portion of the fourth layer which lies between the first and second P-type regions forms a channel of a P-channel HFET; an epitaxially grown N-type anisotype region covering a portion of the sixth layer between and separated from the first and second P-type regions; an epitaxially grown pre-ohmic layer covering the N-type anisotype region; a conductive material formed on top of the pre-ohmic layer making contact with the pre-ohmic layer, wherein the conductive material serves as a gate electrode of the P-channel HFET; electrodes formed on the first and second P-type regions to serve as source-drain electrodes of the P-channel HFET; and an insulating region formed between the N-channel and the P-channel HFET.

Claim 2

Dependent Claim 334 words

A complementary GaAs based heterostructure integrated circuit structure comprising: a semi-insulating GaAs substrate having a major surface; a first epitaxial layer of substantially intrinsic GaAs grown directly over the major surface; a second epitaxially grown layer of substantially intrinsic AlGaAs grown directly over the first layer; a third epitaxially grown layer of substantially intrinsic GaAs grown over the second layer; a fourth epitaxial layer of substantially intrinsic InGaAs grown over the third layer; a fifth epitaxial layer of substantially intrinsic AlAs grown over the fourth layer; a sixth layer of substantially intrinsic AlGaAs grown over the fifth layer; first and second N-type regions formed in the surface of the sixth layer and extending to the third layer, wherein a portion of the fourth layer which lies between the first and second N-type regions forms a channel of an N-channel HFET; a conductive material formed on top of the sixth layer between and separated from the first and second N-type regions and making a rectifying contact with the sixth layer, wherein the conductive material serves as a gate electrode of the N-channel HFET; electrodes formed on the first and second N-type regions to serve as source-drain electrodes of the N-channel HFET; first and second P-type regions formed in the surface of the sixth layer and extending to the third layer, wherein a portion of the fourth layer which lies between the first and second P-type regions forms a channel of a P-channel HFET; an epitaxially grown N-type anisotype region covering a portion of the sixth layer between and separated from the first and second P-type regions; an epitaxially grown pre-ohmic layer covering the N-type anisotype region; a conductive material formed on top of the pre-ohmic layer making contact with the pre-ohmic layer, wherein the conductive material serves as a gate electrode of the P-channel HFET; electrodes formed on the first and second P-type regions to serve as source-drain electrodes of the P-channel HFET; and an insulating region formed between the N-channel and the P-channel HFET.

Claim 3

Dependent Claim 34 words

The integrated circuit of claim 1 wherein the pre-ohmic layer comprises an epitaxially grown layer of substantially intrinsic GaAs, and the contact between the gate electrode and the pre-ohmic layer is a rectifying contact.

Claim 4

Dependent Claim 57 words

The integrated circuit of claim 1 wherein the pre-ohmic layer comprises an epitaxially grown layer of N-type InGaAs which is graded in composition from GaAs at an interface with the anisotype region to a composition of In x Ga 1-x As at an interface with the gate electrode, where x is greater than or equal to 0.5.

Claim 5

Dependent Claim 38 words

The integrated circuit of claim 1 wherein the epitaxially grown N-type anisotype region has a thickness in the range of 200 to 500 angstroms and a substantially uniform doping concentration of at least 5×10 18 atoms/cm 3 .

Claim 6

Dependent Claim 56 words

A complementary HFET structure having N-channel and P-channel HFET devices, the improvement comprising: at least a single delta-doped N-type anisotype layer formed under a gate electrode of the P-channel HFET device; a pre-ohmic layer formed between the N-type anisotype layer and the gate electrode, wherein the gate electrode makes an electrical contact to the pre-ohmic layer.

Claim 7

Dependent Claim 56 words

A complementary HFET structure having N-channel and P-channel HFET devices, the improvement comprising: at least a single delta-doped N-type anisotype layer formed under a gate electrode of the P-channel HFET device; a pre-ohmic layer formed between the N-type anisotype layer and the gate electrode, wherein the gate electrode makes an electrical contact to the pre-ohmic layer.

Claim 8

Dependent Claim 32 words

The HFET of claim 5 wherein the pre-ohmic layer comprises an epitaxially grown layer of substantially intrinsic GaAs and the electrical contact from the gate electrode to the pre-ohmic layer is rectifying.

Claim 9

Dependent Claim 68 words

The HFET of claim 5 wherein the pre-ohmic layer comprises an epitaxially grown layer of N-type InGaAs which is graded in composition from GaAs at an interface with the N-type anisotype layer to a composition of In x Ga 1-x As at an interface with the gate electrode, where x is greater than or equal to 0.5 and the electrical contact to the pre-ohmic layer is substantially ohnmic.

Claim 10

Dependent Claim 31 words

The HFET of claim 5 wherein threshold voltage of the N-channel device is controlled by N-type dopant which is implanted into a channel and a semi-insulating region of the N-channel device.

Claim 11

Dependent Claim 23 words

The HFET of claim 5 wherein the N-channel and P-channel devices are separated by an isolation region comprising an oxygen implanted semiconductor region.

Claim 12

Dependent Claim 97 words

A complementary GaAs heterostructure field effect transistor structure comprising: an N-channel field effect transistor having gate, drain, and source electrodes; a P-channel field effect transistor having gate, drain, and source electrodes; an intrinsic channel region located underneath the gate electrode; a barrier region located between the channel region and the gate electrode; an n-type delta-doped region formed on the barrier region; and an intermediate layer of material coupling the gate electrode of the P-channel device to the n-type delta-doped region, wherein the material for coupling has a bandgap no greater than a bandgap of the delta-doped region.

Claim 13

Dependent Claim 97 words

A complementary GaAs heterostructure field effect transistor structure comprising: an N-channel field effect transistor having gate, drain, and source electrodes; a P-channel field effect transistor having gate, drain, and source electrodes; an intrinsic channel region located underneath the gate electrode; a barrier region located between the channel region and the gate electrode; an n-type delta-doped region formed on the barrier region; and an intermediate layer of material coupling the gate electrode of the P-channel device to the n-type delta-doped region, wherein the material for coupling has a bandgap no greater than a bandgap of the delta-doped region.

Claim 14

Dependent Claim 28 words

The complementary field effect transistor structure of claim 10 wherein the barrier region comprises a layer of intrinsic AlGaAs between the channel region and the N-type delta-doped region.

Claim 15

Dependent Claim 81 words

A P-channel HFET having a gate electrode, a source electrode, a drain electrode, a channel region, and a semi-insulating region formed between the gate electrode and the channel region, the improvement comprising: an N-type region formed underneath the gate electrode and in contact with the semi-insulating region so as to make a rectifying coupling between the gate electrode and the semi-insulating region; and a means for preventing depletion of the N-type region formed between the N-type region and the gate electrode.

Claim 16

Dependent Claim 81 words

A P-channel HFET having a gate electrode, a source electrode, a drain electrode, a channel region, and a semi-insulating region formed between the gate electrode and the channel region, the improvement comprising: an N-type region formed underneath the gate electrode and in contact with the semi-insulating region so as to make a rectifying coupling between the gate electrode and the semi-insulating region; and a means for preventing depletion of the N-type region formed between the N-type region and the gate electrode.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-10-21	1995-04-22	1995-10-22	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-10-21	1999-04-22	1999-10-22	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-10-21	2003-04-22	2003-10-22	$7700.00	Window Closed / Lapsed

Complementary heterojunction field effect transistor with an anisotype N+ ga-channel devices

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