US4899201A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic and optoelectric devices utilizing light hole properties
Assignee: University of Minnesota System
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Filing: 1989-05-31
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Granted: 1990-02-06
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Expires: 2009-05-31
Abstract
Abstract Improved p-channel FETs and optoelectronic devices make use of reduced hole effective mass achieved with quantum confinement. The devices include multiple one-dimensional p-channel FETs which have electrically induced and controllable one dimensional p-type semiconductor wires; square well two-dimensional p-channel FETs; and laser diodes and light emitting diodes which use one dimensional p-type semiconductor wires.
Inventors
- 👤 Jingming Xu
- 👤 Michael Shur
- 👤 Mark Sweeny
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:37
CPC Classifications
H; H10; H10H; H10H20/00; H10H20/80; H10H20/81; H10H20/819; H10H20/821; B; B82; B82Y; B82Y10/00; B82Y20/00; H01; H01S; H01S5/00; H01S5/20; H01S5/22; H01S5/2203; H01S5/30; H01S5/34; H10D; H10D30/00; H10D30/40; H10D30/43; H10D30/47; H10D30/471; H10D30/473; H10D30/4732; H10D84/00; H10D84/01; H10D86/00; H10D86/01; H10H20/062; H01S5/04; H01S5/042; H01S5/0421; H01S5/0422; H01S5/0424
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
161 words
A semiconductor device comprising: a body having a first surface; a first p-type region in the body; a second p-type region in the body spaced from the first p-type region; a hole confinement region in the body generally parallel to the first surface, having a first end connected to the first p-type region and a second end connected to the second p-type region, the hole confinement region confining movement of holes in a direction generally perpendicular to the first surface; and first gate means having a plurality of generally parallel conductive strips which are generally parallel to the first surface and extend in a direction from the first to the second p-type region for creating in the hole confinement region, as a function of an applied electric field, a plurality of generally parallel one-dimensional p-type conducting regions extending between the first and second p-type regions, wherein for each adjacent pair of the conductive strips, a one-dimensional p-type conducting region is induced.
Claim 2
Dependent Claim
161 words
A semiconductor device comprising: a body having a first surface; a first p-type region in the body; a second p-type region in the body spaced from the first p-type region; a hole confinement region in the body generally parallel to the first surface, having a first end connected to the first p-type region and a second end connected to the second p-type region, the hole confinement region confining movement of holes in a direction generally perpendicular to the first surface; and first gate means having a plurality of generally parallel conductive strips which are generally parallel to the first surface and extend in a direction from the first to the second p-type region for creating in the hole confinement region, as a function of an applied electric field, a plurality of generally parallel one-dimensional p-type conducting regions extending between the first and second p-type regions, wherein for each adjacent pair of the conductive strips, a one-dimensional p-type conducting region is induced.
Claim 3
Dependent Claim
24 words
The device of claim 1 wherein the hole confinement region is a p-type channel and is shallow and highly doped relative to the substrate.
Claim 4
Dependent Claim
26 words
The device of claim 1 wherein the hole confinement region is located adjacent a heterojunction formed by first and second semiconductor layers of different band gaps.
Claim 5
Dependent Claim
46 words
The device of claim 1 wherein the body includes a plurality of layers and the hole confinement region is a layer located between layers of semiconductor material, the hole confinement region having a band gap narrower than the band gap of the layers of semiconductor material.
Claim 6
Dependent Claim
41 words
The device of claim 1 and further comprising: second gate means located between the first and second p-type regions and extending in a direction generally transverse to the parallel conductive strips for controlling current flow through the one-dimensional p-type conducting regions.
Claim 7
Dependent Claim
46 words
The device of claim 5 wherein the second gate means has a length, in a direction from the first to the second p-type region, which is less than a length, in a direction from the first to the second p-type region, of the first gate means.
Claim 8
Dependent Claim
136 words
A p-channel FET comprising: a body having a generally planar first surface; a p-type source in the body; a p-type drain in the body and spaced from the source; a hole confinement region generally parallel to the first surface and extending between the source and drain for confining holes in a direction generally perpendicular to the first surface in a square quantum well; gate means for controlling flow of holes in the hole confinement region between the source and the drain; and a pair of conductive strips generally parallel to one another and to the first surface for inducing a 1-D p-type semiconductor wire in the hole confinement region as a function of an applied electric field, the 1-D wire having a first end connected to the source and a second end connected to the drain.
Claim 9
Dependent Claim
136 words
A p-channel FET comprising: a body having a generally planar first surface; a p-type source in the body; a p-type drain in the body and spaced from the source; a hole confinement region generally parallel to the first surface and extending between the source and drain for confining holes in a direction generally perpendicular to the first surface in a square quantum well; gate means for controlling flow of holes in the hole confinement region between the source and the drain; and a pair of conductive strips generally parallel to one another and to the first surface for inducing a 1-D p-type semiconductor wire in the hole confinement region as a function of an applied electric field, the 1-D wire having a first end connected to the source and a second end connected to the drain.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-05 | 1993-08-07 | 1994-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-05 | 1997-08-07 | 1998-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-05 | 2001-08-07 | 2002-02-06 | $7700.00 | Window Closed / Lapsed |