US4463366A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect transistor with combination Schottky-junction gate
Assignee: NTT Inc
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Filing: 1980-06-20
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Granted: 1984-07-31
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Expires: 2000-06-20
Abstract
Abstract A field effect transistor device is constituted by a semiinsulating substrate consisting of a compound semiconductor, an N type semiconductor layer formed on the substrate, a plurality of P type semiconductor gate regions aligned along a straight line and extending through the semiconductor layer to reach the substrate, source and drain electrodes disposed on the semiconductor layer on the opposite sides of the drain regions, a gate electrode having an ohmic contact with the gate regions and having a Schottky contact with the semiconductor layer interposed between the gate regions. Two gate regions on the opposite ends of the array are in contact with the boundary region of the transistor. The field effect transistor device is useful for fabricating an integrated circuit and consumes less electric power. Further it reduces dispersion in the gate pinch off voltage and can be prepared at a high yield.
Inventors
- 👤 Yasunobu Ishii
- 👤 Kazuyoshi Asai
- 👤 Katsuhiko Kurumada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:30
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D30/83
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
163 words
A field effect transistor device comprising a semiinsulating layer made of a compound semiconductor, a compound semiconductor layer of a first conductivity type which is disposed on said semiinsulating layer, at least two semiconductor gate regions of a second conductivity type different from the first conductivity type which extend from a main surface of the semiconductor layer substantially to said semiinsulating layer and which are mutually spaced by a predetermined amount, source and drain electrodes each arranged on opposite sides of said semiconductor gate regions to have an ohmic contact with said compound semiconductor layer of first conductivity type, and a gate electrode means which has an ohmic contact with said semiconductor gate regions and which further has a Schottky contact with the semiconductor layer interposed between the semiconductor gate regions to form at least one Schottky gate region between said semiconductor gate regions, the periphery of the resulting transistor device being in contact with at least two of said semiconductor gate regions.
Claim 2
Dependent Claim
163 words
A field effect transistor device comprising a semiinsulating layer made of a compound semiconductor, a compound semiconductor layer of a first conductivity type which is disposed on said semiinsulating layer, at least two semiconductor gate regions of a second conductivity type different from the first conductivity type which extend from a main surface of the semiconductor layer substantially to said semiinsulating layer and which are mutually spaced by a predetermined amount, source and drain electrodes each arranged on opposite sides of said semiconductor gate regions to have an ohmic contact with said compound semiconductor layer of first conductivity type, and a gate electrode means which has an ohmic contact with said semiconductor gate regions and which further has a Schottky contact with the semiconductor layer interposed between the semiconductor gate regions to form at least one Schottky gate region between said semiconductor gate regions, the periphery of the resulting transistor device being in contact with at least two of said semiconductor gate regions.
Claim 3
Dependent Claim
46 words
The field effect transistor device according to claim 1 wherein on a main surface of the semiconductor gate regions are formed semiconductor gate regions of a type identical with the said semiconductor gate regions but with an impurity concentration higher than the said semiconductor gate regions.
Claim 4
Dependent Claim
52 words
The field effect transistor device according to either claim 1 or 2 wherein a main surface of the semiconductor which is in a Schottky contact with said gate electrode means are formed semiconductor regions of a type identical with the semiconductor layer but with an impurity concentration lower than the semiconductor layer.
References Cited (Backward Citations)
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Cited
US3044909A
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US4297718A
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JPS5273681A
Cited
JPS55141760A
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US4327475A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-07-31 | 1988-01-30 | 1988-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-07-31 | 1992-01-30 | 1992-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-07-31 | 1996-01-30 | 1996-07-31 | $7700.00 | Window Closed / Lapsed |