US4297718A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vertical type field effect transistor
Assignee: Semiconductor Research Foundation
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Filing: 1976-06-08
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Granted: 1981-10-27
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Expires: 1996-06-08
Abstract
Abstract Vertical type field effect transistors are disclosed including one of the highly doped source, gate and drain regions disposed on one of the main opposite faces of one of the semiconductor substrate and the remaining region or regions disposed on the other mainface of the substrate. At least one of the regions is divided into a plurality of elongated slender portions and metallic electrodes are disposed in ohmic contact with the respective regions so as to be identical in configuration to the latter. The highly doped regions themselves may form electrodes.
Inventors
- 👤 Jun-ichi Nishizawa
- 👤 Takashi Kitsuregawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 08:22
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D30/831; H10D99/00; H10P; H10P95/00; H10W; H10W44/00; H10W44/501
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
203 words
A vertical type field effect transistor comprising a semiconductor substrate including a pair of main opposite faces, a source electrode, a gate electrode, and a drain electrode, at least one of said source, gate and drain electrodes being disposed on one of said main opposite faces, at least one of the remaining electrodes being disposed on the other main face of the substrate, an input terminal and an output terminal, wherein at least two highly doped semiconductor regions form respective ones of said electrodes and are formed elongated and slender and having a dimension and impurity concentration imparting thereto a low resistance in a direction of travel of an electromagnetic wave traveling therein to form a transmission line whereby the transistor performs in a traveling wave mode of operation, and wherein said transmission line includes a common line defined by one of said source and gate electrodes, an input line defined by said common line and the other of said source and gate electrodes, and an output line defined by said common line and said drain electrode, and said input and output terminals are disposed on opposite sides of said transistor substrate and respectively connected to said input line and said output line.
Claim 2
Dependent Claim
203 words
A vertical type field effect transistor comprising a semiconductor substrate including a pair of main opposite faces, a source electrode, a gate electrode, and a drain electrode, at least one of said source, gate and drain electrodes being disposed on one of said main opposite faces, at least one of the remaining electrodes being disposed on the other main face of the substrate, an input terminal and an output terminal, wherein at least two highly doped semiconductor regions form respective ones of said electrodes and are formed elongated and slender and having a dimension and impurity concentration imparting thereto a low resistance in a direction of travel of an electromagnetic wave traveling therein to form a transmission line whereby the transistor performs in a traveling wave mode of operation, and wherein said transmission line includes a common line defined by one of said source and gate electrodes, an input line defined by said common line and the other of said source and gate electrodes, and an output line defined by said common line and said drain electrode, and said input and output terminals are disposed on opposite sides of said transistor substrate and respectively connected to said input line and said output line.
Claim 3
Dependent Claim
28 words
A vertical type field effect transistor as claimed in claim 1 wherein said electrodes forming said transmission line are divided into a plurality of parallel elongated slender portions.
Claim 4
Dependent Claim
54 words
A vertical type field effect transistor according to claim 1, wherein said source and gate electrodes are disposed on the same one of the main faces of said substrate, and said drain electrode is disposed on the other main face, and wherein at least said source and said gate electrodes are elongated and slender.
References Cited (Backward Citations)
US3011104A
Cited
US3436689A
Cited
US3663873A
Cited
US3564442A
Cited
US3814995A
Cited
US3905036A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-26 | 1985-04-27 | 1985-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-26 | 1989-04-27 | 1989-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-26 | 1993-04-27 | 1993-10-27 | $7700.00 | Window Closed / Lapsed |