US5084743A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High current, high voltage breakdown field effect transistor
Assignee: North Carolina State University
•
Filing: 1990-03-15
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Granted: 1992-01-28
•
Expires: 2010-03-15
Abstract
Abstract The gate voltage breakdown of an integrated circuit field effect transistor, especially a compound semiconductor metal semiconductor field effect transistor (MESFET) and high electron mobility transistor (HEMT) is dramatically increased by forming an electron trap layer on the surface of the device, under the gate contact and extending beyond the gate contact towards the drain contact. The electron trap layer is preferably a high resisitivity lattice matched monocrystalline layer having at least 10 18 traps per cubic centimeter. For gallium arsenide based transistors, the electron trap layer is preferably formed by low temperature molecular beam epitaxy (MBE) of gallium and arsenic fluxes, to produce a monocrystalline gallium arsenide layer having 1% excess arsenic. For indium phosphide based transistors, the electron trap layer is preferably formed by low temperature MBE of aluminum, indium and arsenic fluxes to produce a monocrystalline aluminum indium arsenide layer having 1% excess arsenic.
Inventors
- 👤 Umesh K. Mishra
- 👤 Robert J. Trew
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:12
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/4732; H10D30/80; H10D30/87; H10D64/00; H10D64/60; H10D64/602
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
132 words
An integrated circuit compound semiconductor metal semiconductor field effect transistor (MESFET) comprising: a compound semiconductor substrate; source and drain regions formed in said compound semiconductor substrate at one face thereof; a channel, formed in said compound semiconductor substrate at said one face, between said source and said drain regions; source, drain and gate contacts for contacting said source, drain and channel, respectively; and a monocrystalline electron trap layer epitaxially formed on said one face between at least part of said gate contact and said channel, and extending beyond said gate contact towards said drain contact, having at least 10 18 electron traps per cubic centimeter for trapping electrons which flow on said face of said compound semiconductor substrate between said gate and drain contacts; whereby said MESFET is resistant to voltage breakdown.
Claim 2
Dependent Claim
132 words
An integrated circuit compound semiconductor metal semiconductor field effect transistor (MESFET) comprising: a compound semiconductor substrate; source and drain regions formed in said compound semiconductor substrate at one face thereof; a channel, formed in said compound semiconductor substrate at said one face, between said source and said drain regions; source, drain and gate contacts for contacting said source, drain and channel, respectively; and a monocrystalline electron trap layer epitaxially formed on said one face between at least part of said gate contact and said channel, and extending beyond said gate contact towards said drain contact, having at least 10 18 electron traps per cubic centimeter for trapping electrons which flow on said face of said compound semiconductor substrate between said gate and drain contacts; whereby said MESFET is resistant to voltage breakdown.
Claim 3
Dependent Claim
38 words
The MESFET of claim 1 wherein said electron trap layer further extends beyond said gate contact towards said source contact, for trapping electrons which flow on said face of said semiconductor substrate between said gate and source contacts.
Claim 4
Dependent Claim
19 words
The MESFET of claim 1 wherein said electron trap layer extends from said gate contact to said drain contact.
Claim 5
Dependent Claim
20 words
The MESFET of claim 1 wherein said electron trap layer further extends beyond said gate contact to said source contact.
Claim 6
Dependent Claim
22 words
The MESFET of claim 1 wherein said electron trap layer comprises between 10 18 and 10 22 electron traps per cubic centimeter.
Claim 7
Dependent Claim
29 words
The MESFET of claim 1 wherein said compound semiconductor substrate comprises monocrystalline gallium arsenide and wherein said electron trap layer comprises a layer of gallium arsenide having excess arsenic.
Claim 8
Dependent Claim
14 words
The MESFET of claim 6 wherein said gallium arsenide layer comprises 1% excess arsenic.
Claim 9
Dependent Claim
28 words
The MESFET of claim 6 further comprising a barrier layer between said electron trap layer and said substrate, for preventing diffusion of the excess arsenic into said substrate.
Claim 10
Dependent Claim
14 words
The MESFET of claim 8 wherein said barrier layer comprises aluminum or aluminum arsenide.
Claim 11
Dependent Claim
30 words
The MESFET of claim 1 wherein said compound semiconductor substrate comprises monocrystalline indium phosphide and wherein said electron trap layer comprises a layer of aluminum indium arsenide having excess arsenic.
Claim 12
Dependent Claim
14 words
The MESFET of claim 10 wherein said aluminum indium arsenide comprises 1% excess arsenic.
Claim 13
Dependent Claim
28 words
The MESFET of claim 10 further comprising a barrier layer between said electron trap layer and said substrate, for preventing diffusion of the excess arsenic into said substrate.
Claim 14
Dependent Claim
14 words
The MESFET of claim 12 wherein said barrier layer comprises aluminum or aluminum arsenide.
Claim 15
Dependent Claim
135 words
An integrated circuit compound semiconductor high electron mobility transistor (HEMT) comprising: a compound semiconductor substrate; source and drain regions formed in said compound semiconductor substrate at one face thereof; a wide and narrow bandgap heterostructure, formed in said compound semiconductor substrate at said one face, between said source and said drain regions; source, drain and gate contacts for contacting said source, drain and heterostructure, respectively; and a monocrystalline electron trap layer epitaxially formed on said one face between at least part of said gate contact and said heterostructure, and extending beyond said gate contact towards said drain contact, having at least 10 18 electron traps per cubic centimeter for trapping electrons which flow on said face of said compound semiconductor substrate between said gate and drain contacts; whereby said HEMT is resistant to voltage breakdown.
Claim 16
Dependent Claim
135 words
An integrated circuit compound semiconductor high electron mobility transistor (HEMT) comprising: a compound semiconductor substrate; source and drain regions formed in said compound semiconductor substrate at one face thereof; a wide and narrow bandgap heterostructure, formed in said compound semiconductor substrate at said one face, between said source and said drain regions; source, drain and gate contacts for contacting said source, drain and heterostructure, respectively; and a monocrystalline electron trap layer epitaxially formed on said one face between at least part of said gate contact and said heterostructure, and extending beyond said gate contact towards said drain contact, having at least 10 18 electron traps per cubic centimeter for trapping electrons which flow on said face of said compound semiconductor substrate between said gate and drain contacts; whereby said HEMT is resistant to voltage breakdown.
Claim 17
Dependent Claim
38 words
The HEMT of claim 14 wherein said electron trap layer further extends beyond said gate contact towards said source contact, for trapping electrons which flow on said face of said semiconductor substrate between said gate and source contacts.
Claim 18
Dependent Claim
19 words
The HEMT of claim 14 wherein said electron trap layer extends from said gate contact to said drain contact.
Claim 19
Dependent Claim
20 words
The HEMT of claim 14 wherein said electron trap layer further extends beyond said gate contact to said source contact.
Claim 20
Dependent Claim
22 words
The HEMT of claim 14 wherein said electron trap layer comprises between 10 18 and 10 22 electron traps per cubic centimeter.
Claim 21
Dependent Claim
29 words
The HEMT of claim 14 wherein said compound semiconductor substrate comprises monocrystalline gallium arsenide and wherein said electron trap layer comprises a layer of gallium arsenide having excess arsenic.
Claim 22
Dependent Claim
14 words
The HEMT of claim 19 wherein said gallium arsenide layer comprises 1% excess arsenic.
Claim 23
Dependent Claim
28 words
The HEMT of claim 19 further comprising a barrier layer between said electron trap layer and said substrate, for preventing diffusion of the excess arsenic into said substrate.
Claim 24
Dependent Claim
14 words
The HEMT of claim 21 wherein said barrier layer comprises aluminum or aluminum arsenide.
Claim 25
Dependent Claim
30 words
The HEMT of claim 14 wherein said compound semiconductor substrate comprises monocrystalline indium phosphide and wherein said electron trap layer comprises a layer of aluminum indium arsenide having excess arsenic.
Claim 26
Dependent Claim
14 words
The HEMT of claim 23 wherein said aluminum indium arsenide comprises 1% excess arsenic.
Claim 27
Dependent Claim
28 words
The HEMT of claim 23 further comprising a barrier layer between said electron trap layer and said substrate, for preventing diffusion of the excess arsenic into said substrate.
Claim 28
Dependent Claim
14 words
The HEMT of claim 25 wherein said barrier layer comprises aluminum or aluminum arsenide.
Claim 29
Dependent Claim
127 words
An integrated circuit field effect transistor comprising: a semiconductor substrate; source and drain regions formed in said semiconductor substrate at one face thereof; a channel, formed in said semiconductor substrate at said one face, between said source and said drain region; source, drain and gate contacts for contacting said source, drain and channel, respectively; and a monocrystalline electron trap layer formed on said one face between at least part of said gate contact and said channel, and extending beyond said gate contact towards said drain contact, and having at least 10 18 electron traps per cubic centimeter for trapping electrons which flow on said face of said semiconductor substrate between said gate and drain contacts; whereby said integrated circuit field effect transistor is resistant to voltage breakdown.
Claim 30
Dependent Claim
127 words
An integrated circuit field effect transistor comprising: a semiconductor substrate; source and drain regions formed in said semiconductor substrate at one face thereof; a channel, formed in said semiconductor substrate at said one face, between said source and said drain region; source, drain and gate contacts for contacting said source, drain and channel, respectively; and a monocrystalline electron trap layer formed on said one face between at least part of said gate contact and said channel, and extending beyond said gate contact towards said drain contact, and having at least 10 18 electron traps per cubic centimeter for trapping electrons which flow on said face of said semiconductor substrate between said gate and drain contacts; whereby said integrated circuit field effect transistor is resistant to voltage breakdown.
Claim 31
Dependent Claim
38 words
The transistor of claim 27 wherein said electron trap layer further extends beyond said gate contact towards said source contact, for trapping electrons which flow on said face of said semiconductor substrate between said gate and source contacts.
Claim 32
Dependent Claim
19 words
The transistor of claim 27 wherein said electron trap layer extends from said gate contact to said drain contact.
Claim 33
Dependent Claim
20 words
The transistor of claim 27 wherein said electron trap layer further extends beyond said gate contact to said source contact.
Claim 34
Dependent Claim
22 words
The transistor of claim 27 wherein said electron trap layer comprises between 10 18 and 10 22 electron traps per cubic centimeter.
Claim 35
Dependent Claim
19 words
The transistor of claim 27 wherein said electron trap layer comprises a layer of gallium arsenide having excess arsenic.
Claim 36
Dependent Claim
14 words
The transistor of claim 27 wherein said gallium arsenide layer comprises 1% excess arsenic.
Claim 37
Dependent Claim
28 words
The transistor of claim 32 wherein said substrate comprises monocrystalline gallium arsenide and wherein said electron trap layer comprises a layer of monocrystalline gallium arsenide having excess arsenic.
Claim 38
Dependent Claim
28 words
The transistor of claim 32 further comprising a barrier layer between said electron trap layer and said substrate, for preventing diffusion of the excess arsenic into said substrate.
Claim 39
Dependent Claim
14 words
The transistor of claim 35 wherein said barrier layer comprises aluminum or aluminum arsenide.
Claim 40
Dependent Claim
16 words
The transistor of claim 27 wherein said transistor comprises a metal semiconductor field effect transistor (MESFET).
Claim 41
Dependent Claim
15 words
The transistor of claim 27 wherein said transistor comprises a high electron mobility transistor (HEMT).
Claim 42
Dependent Claim
20 words
The transistor of claim 27 wherein said electron trap layer comprises a layer of aluminum indium arsenide having excess arsenic.
Claim 43
Dependent Claim
14 words
The transistor of claim 39 wherein said aluminum indium arsenide comprises 1% excess arsenic.
Claim 44
Dependent Claim
29 words
The transistor of claim 39 wherein said substrate comprises monocrystalline indium phosphide and wherein said electron trap layer comprises a layer of monocrystalline aluminum indium arsenide having excess arsenic.
Claim 45
Dependent Claim
28 words
The transistor of claim 39 further comprising a barrier layer between said electron trap layer and said substrate, for preventing diffusion of the excess arsenic into said substrate.
Claim 46
Dependent Claim
14 words
The transistor of claim 41 wherein said barrier layer comprises aluminum or aluminum arsenide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-27 | 1995-07-29 | 1996-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-27 | 1999-07-29 | 2000-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-27 | 2003-07-29 | 2004-01-28 | $7700.00 | Window Closed / Lapsed |