Field effect transistor with active layer apart from guard-ring

Claim 2

In a field effect transistor having a plurality of gate, source and drain region, and gate, source and drain electrodes respectively connected to the gate, source and drain regions, the improvement comprising: (a) a compound semiconducting substrate; (b) a buffer layer provided on said compound semiconducting substrate; (c) an active layer provided on said buffer layer such that said buffer layer is partially covered; (d) a plurality of gate regions embedded in both said buffer layer and said active layer; and (e) a guard-ring connected to said gate regions, said guard-ring being embedded in said buffer layer and apart from said active layer.

Claim 3

An improved field effect transistor as claimed in claim 1, wherein said active layer is positioned higher than said guard-ring when a cross-section of said field effect transistor is viewed from a perspective wherein said compound semiconducting substrate is placed at a bottom portion of said cross-section.

Claim 4

A field effect transistor as claimed in claim 1, wherein said gate regions are connected in parallel by said guard-ring.

Claim 5

In a field effect transistor having a plurality of gate, source and drain regions, and gate, source and drain electrodes respectively connected to the gate, source and drain regions, the improvement comprising: (a) a compound semiconducting substrate; (b) a buffer layer provided on said compound semiconducting substrate; (c) an active layer provided on said buffer layer such that said buffer layer is partially covered; (d) a plurality of gate regions embedded in both said buffer layer and said active layer; and (e) a guard-ring connected to said gate regions, said guard-ring being embedded in said buffer layer and apart from said active layer, wherein said guard-ring surrounds said active layer.

Claim 6

In a field effect transistor having a plurality of gate, source and drain regions, and gate, source and drain electrodes respectively connected to the gate, source and drain regions, the improvement comprising: (a) a compound semiconducting substrate; (b) a buffer layer provided on said compound semiconducting substrate; (c) an active layer provided on said buffer layer such that said buffer layer is partially covered; (d) a plurality of gate regions embedded in both said buffer layer and said active layer; and (e) a guard-ring connected to said gate regions, said guard-ring being embedded in said buffer layer and apart from said active layer, wherein said guard-ring surrounds said active layer.

Claim 7

A field effect transistor as claimed in claim 4, wherein said gate regions are connected in parallel by said guard-ring.

Claim 8

In a PN junction field effect transistor having a plurality of gate, source and drain regions, and gate, source and drain electrodes respectively connected to the gate, source and drain regions, the improvement comprising: (a) a compound semiconducting substrate; (b) a semi-insulating material buffer layer provided on said compound semiconducting substrate; (c) an n-type active layer provided on said buffer layer such that said buffer layer is partially covered; (d) a plurality of p-type gate regions embedded in both said buffer layer and said active layer; and (e) a p-type guard-ring means connected to said gate regions for reducing gate junction capacitance and gate leakage current and for electrically isolating said n-type active region, thereby preventing flow of electric current on a surface of said buffer layer and leakage of electric current from said field effect transistor, (f) said guard-ring means being embedded in said buffer layer and apart from said active layer; wherein (g) said semi-insulating material buffer layer is interposed between said p-type guard-ring means and said n-type active layer to form a PIN junction therewith; and (h) said p-type guard-ring means surrounds said n-type active layer, thereby preventing leakage current from flowing near a surface of said substrate and leakage of electric current within said field effect transistor.

Claim 9

In a PN junction field effect transistor having a plurality of gate, source and drain regions, and gate, source and drain electrodes respectively connected to the gate, source and drain regions, the improvement comprising: (a) a compound semiconducting substrate; (b) a semi-insulating material buffer layer provided on said compound semiconducting substrate; (c) an n-type active layer provided on said buffer layer such that said buffer layer is partially covered; (d) a plurality of p-type gate regions embedded in both said buffer layer and said active layer; and (e) a p-type guard-ring means connected to said gate regions for reducing gate junction capacitance and gate leakage current and for electrically isolating said n-type active region, thereby preventing flow of electric current on a surface of said buffer layer and leakage of electric current from said field effect transistor, (f) said guard-ring means being embedded in said buffer layer and apart from said active layer; wherein (g) said semi-insulating material buffer layer is interposed between said p-type guard-ring means and said n-type active layer to form a PIN junction therewith; and (h) said p-type guard-ring means surrounds said n-type active layer, thereby preventing leakage current from flowing near a surface of said substrate and leakage of electric current within said field effect transistor.