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JPS58145166A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Fujitsu Ltd
•
Filing: 1982-02-24
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Granted: —
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Expires: 2002-02-24
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Abstract

Abstract PURPOSE:To prevent the adverse effect of gate pad potential on channel currents between source-drain, and obviate the degradation of element characteristics by implanting atoms giving no conductivity such as protons to the gate-pad forming region of a high-resistance substrate and forming an insulating layer. CONSTITUTION:The substrate is mesa-etched for isolation, and protons are implanted in the region 5 through an ion implantation method. A source electrode S, a gate electrode G, a drain electrode D, a gate pad 4 and a drain pad 3 are formed after protons are implanted. The conditions of the implantation of protons for forming the insulating layer are acceleration energy of 300KeV and the quantity of douse of 1X10<14>cm<-2> when a GaAs MES FET is manufactured. Such conditions for implantation are changed in response to element characteristics, and a value through which the insulating layer through which the best effect is obtained can be formed is selected. The depth of the insulating layer can be controlled by the energy of implantation.

Inventors

  • 👤 Masashi Ozeki
  • 👤 尾関 雅志
  • 👤 Akihiro Shibatomi
  • 👤 昭洋 柴富

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 17:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80

Claims Analysis

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References Cited (Backward Citations)

JPS5321581A Cited

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