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US5079620A Expired / Lapsed US ⏱️ 0.0 years remaining

Split-gate field effect transistor

Assignee: University of Minnesota System
•
Filing: 1991-03-04
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Granted: 1992-01-07
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Expires: 2011-03-04
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Abstract

Abstract A field effect transistor having a gate voltage swing in the transistor channel varying as a function of position between the drain and the source. The gate voltage swing in the transistor channel may be made to vary as a function of position by making the threshold voltage a function of position. Alternatively, a split-gate device may be used by applying a voltage between the gates. In both cases, the electric field near the source is raised to accelerate the electrons thereby decreasing electron transit time.

Inventors

  • 👤 Michael Shur

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 00:34
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D30/80; H10D30/87; H10D30/873; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 122 words
A field effect transistor comprising: a drain region including a drain contact; a source region including a source contact; a single n channel region including at least one gate contact, the n channel region extending between the drain region and the source region, the n channel region having a depth; and an ion implantation region in the n channel region adjacent the drain region, the ion implantation region extending into the n channel region to a common depth with the n channel region, wherein V t in the n channel region is less positive in the ion implantation region of the n channel region than it is in the remainder of the n channel region which is outside the ion implantation region.
Claim 2
Dependent Claim 122 words
A field effect transistor comprising: a drain region including a drain contact; a source region including a source contact; a single n channel region including at least one gate contact, the n channel region extending between the drain region and the source region, the n channel region having a depth; and an ion implantation region in the n channel region adjacent the drain region, the ion implantation region extending into the n channel region to a common depth with the n channel region, wherein V t in the n channel region is less positive in the ion implantation region of the n channel region than it is in the remainder of the n channel region which is outside the ion implantation region.
Claim 3
Dependent Claim 122 words
A field effect transistor comprising: a drain region including a drain contact; a source region including a source contact; a single p channel region including at least one gate contact, the p channel region extending between the drain region and the source region, the p channel region having a depth; and an ion implantation region in the p channel region adjacent the drain region, the ion implantation region extending into the p channel region to a common depth with the p channel region, wherein V t in the p channel region is less negative in the ion implantation region of the p channel region than it is in the remainder of the p channel region which is outside the ion implantation region.
Claim 4
Dependent Claim 122 words
A field effect transistor comprising: a drain region including a drain contact; a source region including a source contact; a single p channel region including at least one gate contact, the p channel region extending between the drain region and the source region, the p channel region having a depth; and an ion implantation region in the p channel region adjacent the drain region, the ion implantation region extending into the p channel region to a common depth with the p channel region, wherein V t in the p channel region is less negative in the ion implantation region of the p channel region than it is in the remainder of the p channel region which is outside the ion implantation region.

References Cited (Backward Citations)

US3333168A Cited
US3436623A Cited
US3714522A Cited
US4814839A Cited
US4395725A Cited
JPS59200465A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-01-06 1995-07-08 1996-01-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-01-06 1999-07-08 2000-01-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-01-06 2003-07-08 2004-01-07 $7700.00 Window Closed / Lapsed

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