Patent US5329152A successfully refreshed from Google Patents.
US5329152A
Expired / Lapsed
US
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Ablative etch resistant coating for laser personalization of integrated circuits
Assignee: Quick Tech Ltd
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Filing: 1992-01-24
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Granted: 1994-07-12
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Expires: 2012-01-24
Abstract
Abstract A programmable integrated circuit for prototyping applications including a first patterned metal layer, an insulation layer formed over the first metal layer and a second patterned metal layer formed over the insulation layer, the first and second patterned metal layers being formed with selectably removable regions, the insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions a coating comprising a layer of a dielectric material of high laser radiation absorption coefficient.
Inventors
- 👤 Meir I. Janai
- 👤 Zvi Orbach
- 👤 Alon Kapel
- 👤 Sharon Zehavi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:06
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10W20/494; H10W20/01; H10W20/031; H10W20/067; H10W20/068
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
97 words
A semiconductor device comprising: a first patterned metal layer; an insulation layer formed over the first metal layer; and a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions; said insulation layer being formed with apertures overlying at least some of the selectively removable regions, and there being formed over the selectably removable regions an ablative triple layer coating comprising a layer of silicon oxide over which is formed a layer of silicon nitride and over which is formed a layer of amorphous silicon.
Claim 2
Dependent Claim
97 words
A semiconductor device comprising: a first patterned metal layer; an insulation layer formed over the first metal layer; and a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions; said insulation layer being formed with apertures overlying at least some of the selectively removable regions, and there being formed over the selectably removable regions an ablative triple layer coating comprising a layer of silicon oxide over which is formed a layer of silicon nitride and over which is formed a layer of amorphous silicon.
Claim 3
Dependent Claim
20 words
Apparatus according to claim 1 and wherein the silicon oxide layer has a thickness of between 1000 and 3000 angstrom.
Claim 4
Dependent Claim
27 words
Apparatus according to claim 1 and wherein the amorphous silicon layer contains up to 30% atomic weight of at least one of Hydrogen, Carbon, Nitrogen and Oxygen.
Claim 5
Dependent Claim
26 words
Apparatus according to claim 1 and wherein the silicon oxide layer contains up to 10% atomic weight of at least one of arsenic, phosphorous and boron.
Claim 6
Dependent Claim
87 words
A semiconductor device comprising: a first patterned metal layer; an insulated layer formed over the first metal layer; and a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions, said insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions an ablative multi-layer coating comprising first and second dielectric layers having different etchability and thereover a layer of amorphous silicon.
Claim 7
Dependent Claim
87 words
A semiconductor device comprising: a first patterned metal layer; an insulated layer formed over the first metal layer; and a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions, said insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions an ablative multi-layer coating comprising first and second dielectric layers having different etchability and thereover a layer of amorphous silicon.
Claim 8
Dependent Claim
17 words
Apparatus according to claim 5 and wherein at least one of said dielectric layers comprises silicon nitride.
Claim 9
Dependent Claim
27 words
Apparatus according to claim 5 and wherein the amorphous silicon layer contains up to 30% atomic weight of at least one of Hydrogen, Carbon, Nitrogen and Oxygen.
Claim 10
Dependent Claim
20 words
Apparatus according to claim 5 and wherein said apertures overlie removable regions on both said first and second metal layers.
Claim 11
Dependent Claim
15 words
Apparatus according to claim 5 and wherein said first dielectric layer comprises a planarization layer.
Claim 12
Dependent Claim
14 words
Apparatus according to claim 9 and wherein said planarization layer comprises a polymeric substance.
Claim 13
Dependent Claim
15 words
Apparatus according to claim 9 and wherein said planarization layer comprises a spin-on glass layer.
Claim 14
Dependent Claim
87 words
A semiconductor device comprising: a first patterned metal layer; an insulation layer formed over the first metal layer; a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions, said insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions an ablative multi-layer dielectric coating comprising a dielectric layer and thereover a layer of laser energy absorbing material comprising amorphous silicon.
Claim 15
Dependent Claim
87 words
A semiconductor device comprising: a first patterned metal layer; an insulation layer formed over the first metal layer; a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions, said insulation layer being formed with apertures overlying at least some of the selectably removable regions, and there being formed over the selectably removable regions an ablative multi-layer dielectric coating comprising a dielectric layer and thereover a layer of laser energy absorbing material comprising amorphous silicon.
Claim 16
Dependent Claim
27 words
Apparatus according to claim 12 and wherein the amorphous silicon layer contains up to 30% atomic weight of at least one of Hydrogen, Carbon, Nitrogen and Oxygen.
Claim 17
Dependent Claim
66 words
A semiconductor device comprising: a first patterned metal layer; an insulation layer formed over the first metal layer; and a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions, and there being formed over the selectably removable regions an ablative multi-layer coating comprising a dielectric layer and thereover a layer of amorphous silicon.
Claim 18
Dependent Claim
66 words
A semiconductor device comprising: a first patterned metal layer; an insulation layer formed over the first metal layer; and a second patterned metal layer formed over the insulation layer; said first and second patterned metal layers being formed with selectably removable regions, and there being formed over the selectably removable regions an ablative multi-layer coating comprising a dielectric layer and thereover a layer of amorphous silicon.
Claim 19
Dependent Claim
17 words
Apparatus according to claim 14 and wherein said dielectric layer comprises silicon oxide, silicon nitride, or polyimide.
Claim 20
Dependent Claim
27 words
Apparatus according to claim 14 and wherein the amorphous silicon layer contains up to 30% atomic weight of at least one of Hydrogen, Carbon, Nitrogen and Oxygen.
Claim 21
Dependent Claim
25 words
Apparatus according to claim 16 and wherein said dielectric layer contains up to 10% atomic weight of at least one of arsenic, phosphorous and boron.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |