Redundancy fuse reading circuit for integrated memory

Claim 2

An integrated circuit memory comprising: a redundancy circuit with at least one battery of fuses defining an address of a defective element and circuitry to put a repair element into operation when an address applied to the memory corresponds to an address stored in said battery of fuses, said redundancy circuit comprising, associated with each fuse, a current-voltage converter having an input connected to said fuse, said converter comprising a first inverter, the input of which constitutes the input of said converter and the output of which controls the gate of a feedback transistor, said feedback transistor having a source connected to a supply voltage and a drain connected to said input of said inverter; and further comprising first and second additional inverters in series between said output of said first inverter and said gate of said feedback transistor, said additional inverters each being highly asymmetrical transistors in opposite respective directions.

Claim 3

An integrated circuit memory according to claim 1, wherein said first additional inverter comprises a transistor with a first type of conductivity having a channel width-to-length ratio far greater than 1, and a transistor with a second type of conductivity having a channel width-to-length ratio which is far smaller than 1.

Claim 4

An integrated circuit memory according to claim 1, wherein said second additional inverter comprises a transistor with a first type of conductivity having a channel width-to-length ratio far smaller than 1, and a transistor with a second type of conductivity, having a channel width-to-length ratio far greater than 1.

Claim 5

A memory according to claim 1, wherein said feedback transistor is a P channel MOS transistor, wherein the first inverter comprises a P channel transistor with a big channel width-to-length ratio and an N channel transistor with a small channel width-to-length ratio, and wherein the second inverter comprises a P channel transistor with a small channel width-to-length ratio and an N channel transistor with a big channel width-to-length ratio.

Claim 6

The memory of claim 1, wherein said first inverter is directly connected to be driven by said reading node.

Claim 7

The memory of claim 1, wherein said second inverter is directly connected to be driven by said first inverter.

Claim 8

A circuit for reading the binary state of a cell, comprising an inverter connected to the cell and a feedback transistor, the source of which is connected to a supply voltage, and the drain of which is connected to the input of the inverter, wherein the output of the inverter is connected to the gate of the transistor by means of two inverters in series, each comprising two high asymmetrical transistors, the asymmetry being in reverse for the two inverters.

Claim 9

A circuit for reading the binary state of a cell, comprising an inverter connected to the cell and a feedback transistor, the source of which is connected to a supply voltage, and the drain of which is connected to the input of the inverter, wherein the output of the inverter is connected to the gate of the transistor by means of two inverters in series, each comprising two high asymmetrical transistors, the asymmetry being in reverse for the two inverters.

Claim 10

A reading circuit according to claim 7, wherein the first of said additional inverters comprises a P channel transistor with a large channel width-to-length ratio and an N channel transistor with a small channel width-to-length ratio, and wherein second said additional inverter comprises a P channel transistor with a small channel width-to-length ratio and an N channel transistor with a large channel width-to-length ratio.

Claim 11

An integrated circuit memory, comprising: an array of memory cells; address decoding circuitry connected to receive externally generated addresses, and accordingly to access cells from said array; redundant element portions, each including multiple memory cells corresponding to a subset of said cells of said array; redundancy substitution circuitry, comprising multiple sets of nonvolatile memory cells, and match detection logic connected to receive at least some bits of said externally generated addresses and to check for matches with defect location addresses stored in said nonvolatile memory cells; wherein at least some ones of said nonvolatile memory cells each include: an n-channel floating-gate transistor, connected to sink current from a respective reading node; a first inverter operatively connected to be driven by said reading node; a second inverter operatively connected to receive an output from said first inverter, and a third inverter directly connected to receive an output from said second inverter; and a P-channel feedback transistor connected between said reading node and a scond power supply, and having a gate directly connected to be driven by an output of said third inverter; wherein said third inverter comprises an NMOS and a PMOS transistor, with said NMOS transistor being much stronger than said PMOS transistor; and wherein said secoind inverter comprises an NMOS and a PMOS transistor, with said PMOS transistor being much stronger than said NMOS transistor.

Claim 12

An integrated circuit memory, comprising: an array of memory cells; address decoding circuitry connected to receive externally generated addresses, and accordingly to access cells from said array; redundant element portions, each including multiple memory cells corresponding to a subset of said cells of said array; redundancy substitution circuitry, comprising multiple sets of nonvolatile memory cells, and match detection logic connected to receive at least some bits of said externally generated addresses and to check for matches with defect location addresses stored in said nonvolatile memory cells; wherein at least some ones of said nonvolatile memory cells each include: an n-channel floating-gate transistor, connected to sink current from a respective reading node; a first inverter operatively connected to be driven by said reading node; a second inverter operatively connected to receive an output from said first inverter, and a third inverter directly connected to receive an output from said second inverter; and a P-channel feedback transistor connected between said reading node and a scond power supply, and having a gate directly connected to be driven by an output of said third inverter; wherein said third inverter comprises an NMOS and a PMOS transistor, with said NMOS transistor being much stronger than said PMOS transistor; and wherein said secoind inverter comprises an NMOS and a PMOS transistor, with said PMOS transistor being much stronger than said NMOS transistor.

Claim 13

The memory of claim 9, wherein said first inverter is directly connected to be driven by said reading node.

Claim 14

The memory of claim 9, wherein said second inverter is directly connected to be driven by said first inverter.

Claim 15

An integrated circuit memory, comprising: an array of memory cells; address decoding circuitry connected to receive externally generated addresses, and accordingly to access cells from said array; redundant element portions, each including multiple memory cells corresponding to a subset of said cells of said array; redundancy substitution circuitry, comprising multiple sets of nonvolatile memory cells, and match detection logic connected to receive at lest some bits of said externally generated addresses and to check for matches with defect location addresses stored in said nonvolatile memory cells; wherein at least some ones of said nonvolatile memory cells each include: a programmable transistor, connected to pass current from a first power supply voltage to a respective reading node; a first inverter operatively connected to be driven in accordance with the state of said reading node; a second inverter connected to receive an output from said first inverter, and a third inverter connected to receive an output from said second inverter; and a feedback transistor connected between said reading node and a second power supply, and connected to be driven by an output of said third inverter; wherein said third inverter comprises a first transistor connected to said first power supply, and a second transistor connected to said second power supply; said first transistor being much stronger than said second transistor.

Claim 16

An integrated circuit memory, comprising: an array of memory cells; address decoding circuitry connected to receive externally generated addresses, and accordingly to access cells from said array; redundant element portions, each including multiple memory cells corresponding to a subset of said cells of said array; redundancy substitution circuitry, comprising multiple sets of nonvolatile memory cells, and match detection logic connected to receive at lest some bits of said externally generated addresses and to check for matches with defect location addresses stored in said nonvolatile memory cells; wherein at least some ones of said nonvolatile memory cells each include: a programmable transistor, connected to pass current from a first power supply voltage to a respective reading node; a first inverter operatively connected to be driven in accordance with the state of said reading node; a second inverter connected to receive an output from said first inverter, and a third inverter connected to receive an output from said second inverter; and a feedback transistor connected between said reading node and a second power supply, and connected to be driven by an output of said third inverter; wherein said third inverter comprises a first transistor connected to said first power supply, and a second transistor connected to said second power supply; said first transistor being much stronger than said second transistor.

Claim 17

The memory of claim 12 wherein said first inverter is directly connected to be driven by said reading node.

Claim 18

The memory of claim 12, wherein said second inverter is directly connected to be driven by said first inverter.