Reset signal generating circuit

Claim 2

A reset signal generating circuit comprising: voltage dividing means for dividing a power source voltage into a divided voltage; first switching means coupled to said voltage dividing means, said first switching means being turned ON when the power source voltage rises to a value in a vicinity of a predetermined value with an arbitrary rising speed; second switching means coupled to an output of said first switching means, said second switching means having a transistor which has an input electrode for receiving an output signal of said first switching means, an output electrode and a control electrode, and control means coupled between said input electrode and said control electrode for turning said transistor ON in response to an output signal of said first switching means, said transistor being turned ON during a time in which said first switching means is ON; and charging and discharging means coupled to said output electrode of said second switching means having a capacitor which is supplied with an output signal of said second switching means for starting a charging operation from a first time when said second switching means turns ON, said capacitor being charged by a current which flows through said transistor of said second switching means during a charging operation, said charging and discharging means for outputting a reset signal for a constant time from said first time to a second time and for stopping to output a reset signal after said second time.

Claim 3

A reset signal generating circuit as claimed in claim 1 wherein said first switching means includes a switch supplied with the power source voltage and a load coupled between said switch and a ground voltage, said switch outputting the power source voltage as the output signal of said first switching means when said first switching means is turned ON.

Claim 4

A reset signal generating circuit as claimed in claim 1, wherein said transistor of said second switching means outputs said output signal of said first switching means when said first switching means is turned ON.

Claim 5

A reset signal generating circuit as claimed in claim 1, wherein said transistor of said second switching means includes a metal oxide semiconductor (MOS) transistor having a source supplied with said output signal of said first switching means, said control means of said second switching means further having a first inverter supplied with said output signal of said first switching means, a first capacitor having one terminal supplied with the power source voltage and another terminal coupled to an output terminal of said first inverter, a second inverter supplied with an output signal of said first inverter, and a second capacitor having one terminal coupled to an output terminal of said second inverter and another terminal coupled to a ground, said output terminal of said second inverter being coupled to a gate of said MOS transistor, said output signal of said second switching means being obtained from a drain of said MOS transistor.

Claim 6

A reset signal generating circuit as claimed in claim 4, wherein said charging and discharging means starts a discharging operation when said power source voltage falls under a certain value after said second time, said first switching means including a switch supplied with the power source voltage and a load coupled between said switch and the ground, said switch outputting the power source voltage as the output signal of said first switching means when said first switching means is turned ON, said discharge operation being a discharge of said capacitor to the ground through a pn junction of said MOS transistor and said load.

Claim 7

A reset signal generating circuit as claimed in claim 1 wherein said charging and discharging means further includes a logic circuit which outputs the reset signal after carrying out a logic operation on an output signal of said capacitor.

Claim 8

A reset signal generating circuit as claimed in claim 6, wherein said charging and discharging means continues to output the reset signal until a terminal voltage of said capacitor reaches a threshold value of said logic circuit.

Claim 9

A reset signal generating circuit as claimed in claim 1, wherein said circuit is provided within a semiconductor device which comprises an internal circuit, said reset signal being supplied to the internal circuit.

Claim 10

A reset signal generating circuit comprising: voltage dividing means for dividing a power source voltage into a divided voltage; first switching means coupled to said voltage dividing means, said first switching means being turned ON when the power source voltage rises to a value in a vicinity of a predetermined value with an arbitrary rising speed; second switching means coupled to an output of said first switching means, said second switching means being turned ON during a time in which said first switching means is ON; and charging and discharging means including a capacitor which is supplied with an output signal of said second switching means for starting a charging operation from a first time when said second switching means turns ON, said charging and discharging means outputting a reset signal for a constant time from said first time to a second time and stopping to output the reset signal after said second time, said second switching means including a metal oxide semiconductor (MOS) transistor having a source supplied with the output signal of said first switching means, a first inverter supplied with the output signal of said first switching means, a first capacitor having one terminal supplied with the power source voltage and another terminal coupled to an output terminal of said first inverter, a second inverter supplied with an output signal of said first inverter, and a second capacitor having one terminal coupled to an output terminal of said second inverter and another terminal coupled to a ground, said output terminal of said second inverter being coupled to a gate of said MOS transistor, said output signal of said second switching means being obtained from a drain of said MOS transistor.

Claim 11

A reset signal generating circuit comprising: voltage dividing means for dividing a power source voltage into a divided voltage; first switching means coupled to said voltage dividing means, said first switching means being turned ON when the power source voltage rises to a value in a vicinity of a predetermined value with an arbitrary rising speed; second switching means coupled to an output of said first switching means, said second switching means being turned ON during a time in which said first switching means is ON; and charging and discharging means including a capacitor which is supplied with an output signal of said second switching means for starting a charging operation from a first time when said second switching means turns ON, said charging and discharging means outputting a reset signal for a constant time from said first time to a second time and stopping to output the reset signal after said second time, said second switching means including a metal oxide semiconductor (MOS) transistor having a source supplied with the output signal of said first switching means, a first inverter supplied with the output signal of said first switching means, a first capacitor having one terminal supplied with the power source voltage and another terminal coupled to an output terminal of said first inverter, a second inverter supplied with an output signal of said first inverter, and a second capacitor having one terminal coupled to an output terminal of said second inverter and another terminal coupled to a ground, said output terminal of said second inverter being coupled to a gate of said MOS transistor, said output signal of said second switching means being obtained from a drain of said MOS transistor.

Claim 12

A reset signal generating circuit as claimed in claim 9, wherein said charging and discharging means starts a discharging operation when the power source voltage falls under a certain value after said second time, said first switching means including a switch supplied with the power source voltage and a load coupled between said switch and the ground, said switch outputting the power source voltage as the output signal of said first switching means when said first switching means is turned ON, said discharge operation being a discharge of said capacitor to the ground through a pn junction of said MOS transistor and said load.