CMOS power-on reset circuit

Claim 2

A circuit for providing a reset pulse comprising: receiving means for receiving a supply voltage and providing a first output; latching means coupled to said supply voltage, said latching means providing a second output, said second output coupled to said receiving means; filter means coupled to said first output, said second output, and said supply voltage, said filter means providing a third output; wave shaping means coupled to said supply voltage and said third output, said wave shaping means providing said reset pulse, said reset pulse coupled to said latching means.

Claim 3

The circuit of claim 1 wherein said receiving means comprises an intermediate level reference generator.

Claim 4

The circuit of claim 1 wherein said latching means is used to prevent unintentional occurrence of said reset pulse.

Claim 5

The circuit of claim 2, wherein said intermediate level reference generator comprises three field-effect transistors (FETs) of a first type, and one FET of a second type, where: said three FETs of said first type are connected in series; said FET of said second type is connected in parallel with one of said three series-connected FETs; one of said FETs of said first type enables said intermediate level reference generator when said second output falls below a first voltage level; said FET of said second type disables said intermediate level reference generator when said second output exceeds a second voltage level.

Claim 6

The circuit of claim 1, wherein said filter means comprises an RC filter comprising two FETs of said second type, a capacitor of a first type and a capacitor of a second type, where: said FETs are connected in parallel; said capacitor of said second type is connected in parallel between said first output and a low voltage level; said capacitor of said first type is connected in series between said supply voltage and drains of said FETs connected in parallel; one of said FETs receiving at a gate said first output; one of said FETs receiving at a gate said second output.

Claim 7

The circuit of claim 1, wherein said wave shaping means comprises four complementary pairs of FET's, where: said complementary pairs comprise a FET of said first type connected in series with a FET of said second type; said complementary pairs provide a first complementary pair output, a second complementary pair output, a third complementary pair output and a fourth complementary pair output, respectively; said complementary pairs are connected in parallel between said supply voltage and a low voltage level; said third output of the filter is connected to gates of a first of said complementary pairs, said first complementary pair output connected to gates of a second of said complementary pairs, said second complementary pair output connected to gates of a third of said complementary pairs, said third complementary pair output connected to the gates of a fourth of said complementary pairs, said fourth complementary pair output providing said reset pulse; said reset pulse set at said low voltage level when said third output is below a first voltage level; said reset pulse is approximately equal to said supply voltage when said third output is above said first voltage level.

Claim 8

The circuit of claim 3, wherein said latching means comprise a FET of said first type, a FET of said second type and a capacitor of said second type, where: said FET's are connected in series between said supply voltage and a low voltage level; said capacitor is connected to drains of said FET's; said reset pulse is coupled to gates of said FET's; drains of said FET's providing said second output; said second output is at said low voltage level when said reset pulse is above a first voltage level; said second output of said latching means matches said first output when said input received from said wave shaping means is below said first voltage level.

Claim 9

The circuit of claim 6, wherein two of said series complementary pairs are connected through a resistor to said supply voltage.

Claim 10

The circuit of claim 6, wherein said reset pulse is connected to a first and second inverter.