US4818904A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power on reset pulse generating circuit sensitive to rise time of the power supply
Assignee: Mitsubishi Electric Corp
•
Filing: 1988-01-13
•
Granted: 1989-04-04
•
Expires: 2008-01-13
Abstract
Abstract A power on reset pulse generating circuit, which comprises a flip-flop coupled through capacitors to an applied supply voltage to be resettable thereby, a time constant circuit including an array of diode connecting MOS transistors and a capacitor coupled to reset the flip-flop in response to a fast rise time of an applied supply voltage, and another MOS transistor connected to detect a level of a voltage at the output terminal to reset the flip-flop in response to a slow rise time of the applied supply voltage.
Inventors
- 👤 Toshifumi Kobayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 06:38
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
94 words
A power on reset pulse generating circuit for providing a reset signal at an output terminal thereof, comprising: latch means settable into a first state and resettable into a second state, means for setting said latch means in response to an applied supply voltage, first resetting means including time constant circuit means for resetting said latch means in response to an applied supply voltage having a fast rise time, and second resetting means including level detecting means for resetting said latch means in response to an applied supply voltage having a slow rise time.
Claim 2
Dependent Claim
94 words
A power on reset pulse generating circuit for providing a reset signal at an output terminal thereof, comprising: latch means settable into a first state and resettable into a second state, means for setting said latch means in response to an applied supply voltage, first resetting means including time constant circuit means for resetting said latch means in response to an applied supply voltage having a fast rise time, and second resetting means including level detecting means for resetting said latch means in response to an applied supply voltage having a slow rise time.
Claim 3
Dependent Claim
20 words
A power on reset pulse generating circuit in accordance with claim 1, wherein said latch means comprises cross coupled inverters.
Claim 4
Dependent Claim
33 words
A power on reset pulse generating circuit in accordance with claim 1, wherein said setting means comprises first capacitor means connected between said latch means and a source of said applied supply voltage.
Claim 5
Dependent Claim
28 words
A power on reset pulse generating circuit in accordance with claim 3, wherein said setting means includes second capacitor means connected between said latch means and a ground.
Claim 6
Dependent Claim
32 words
A power on reset pulse generating circuit in accordance with claim 1, wherein said first resetting means comprises resistance means and third capacitor means coupled between said output terminal and a ground.
Claim 7
Dependent Claim
20 words
A power on reset pulse generating circuit in accordance with claim 5, wherein said resistance means comprises MOS transistor means.
Claim 8
Dependent Claim
29 words
A power on reset pulse generating circuit in accordance with claim 6, wherein said MOS transistor means comprises a plurality of MOS transistors connected in series with each other.
Claim 9
Dependent Claim
32 words
A power on reset pulse generating circuit in accordance with claim 1, wherein said second resetting means comprises level detecting means for detecting a level of a voltage at said output terminal.
Claim 10
Dependent Claim
44 words
A power on reset pulse generating circuit in accordance with claim 8, wherein said level detecting means comprises first transistor means connected between said latch means and a ground, and constant voltage dropping means connected between said output terminal and said first transistor means.
Claim 11
Dependent Claim
24 words
A power on reset pulse generating circuit in accordance with claim 9, wherein said constant voltage dropping means comprises diode connected MOS transistor means.
Claim 12
Dependent Claim
47 words
A power on reset pulse generating circuit in accordance with claim 1, wherein said time constant circuit means of said second resetting means includes a capacitor, said reset pulse generating circuit further including means responsive to the reset state of said latch means for discharging said capacitor.
Claim 13
Dependent Claim
43 words
A power on reset pulse generating circuit in accordance with claim 1, which further includes resettable circuit means reset in response to said reset signal, said resettable circuit means and said power on reset pulse generating circuit being integrated on a common chip.
Claim 14
Independent Claim
99 words
A method of providing a power on reset pulse at an output terminal, comprising the steps of detecting an applied supply voltage, setting latch means in a first state in response to said applied supply voltage, using time constant circuit means coupled to said output terminal for resetting said latch means in a second state in response to a fast rise time of said applied supply voltage, and using voltage level detecting means coupled to said output terminal for resetting said latch means into said second state in response to a slow rise time of said applied supply voltage.
Claim 15
Independent Claim
99 words
A method of providing a power on reset pulse at an output terminal, comprising the steps of detecting an applied supply voltage, setting latch means in a first state in response to said applied supply voltage, using time constant circuit means coupled to said output terminal for resetting said latch means in a second state in response to a fast rise time of said applied supply voltage, and using voltage level detecting means coupled to said output terminal for resetting said latch means into said second state in response to a slow rise time of said applied supply voltage.
References Cited (Backward Citations)
US4045688A
Cited
US4210829A
Cited
JPS60162308A
Cited
US4591745A
Cited
US4581552A
Cited
JPS60250715A
Cited
US4634904A
Cited
US4716322A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-03 | 1992-10-03 | 1993-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-03 | 1996-10-03 | 1997-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-03 | 2000-10-03 | 2001-04-04 | $7700.00 | Window Closed / Lapsed |