US5157630A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory which can be prevented from shifting to undesired operation mode
Assignee: Mitsubishi Electric Corp
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Filing: 1990-12-21
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Granted: 1992-10-20
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Expires: 2010-12-21
Abstract
Abstract Disclosed are an RAS input circuit (100a) and a CAS input circuit (200a) applicable to a dynamic random access memory (DRAM). The threshold voltage V TRAS of the RAS input circuit and the threshold voltage V TCAS of the CAS input circuit are settled to satisfy the relation V TRAS >V TCAS . Therefore, a L level of an external RAS signal is more easily determined by a L level of an external CAS signal. As a result, the DRAM is prevented from erroneously starting its operation under a test mode without an external request.
Inventors
- 👤 Makoto Suwa
- 👤 Hiroshi Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:29
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
221 words
A semiconductor memory operable under a predetermined operation mode designated by a combination of externally applied first and second state control signals (CAS, RAS), said first and second state control signals taking first and second logics (L, H), respectively, according to their potentials, said semiconductor memory comprising: first determining means (22a) connected to receive the first state control signal for determining a logic of the first state control signal; second determining means (21a) connected to receive the second state control signal for determining a logic of the second state control signal; operation mode detecting means (14) responsive to said first and second determining means for detecting the designation of said predetermined operation mode; said operation mode detecting means detecting said first determining means determining the first logic of the first state control signal and said second determining means determining a change of the second state control signal from the second logic to the first logic, said semiconductor memory starting its operation under said predetermined operation mode in response to said operation mode detecting means, and facilitating means (W11, W12, W21, W22) for facilitating the determination of the first logic of the second state control signal more than the determination of the first logic of the first state control signal by controlling the threshold levels of said first and second determining means.
Claim 2
Dependent Claim
221 words
A semiconductor memory operable under a predetermined operation mode designated by a combination of externally applied first and second state control signals (CAS, RAS), said first and second state control signals taking first and second logics (L, H), respectively, according to their potentials, said semiconductor memory comprising: first determining means (22a) connected to receive the first state control signal for determining a logic of the first state control signal; second determining means (21a) connected to receive the second state control signal for determining a logic of the second state control signal; operation mode detecting means (14) responsive to said first and second determining means for detecting the designation of said predetermined operation mode; said operation mode detecting means detecting said first determining means determining the first logic of the first state control signal and said second determining means determining a change of the second state control signal from the second logic to the first logic, said semiconductor memory starting its operation under said predetermined operation mode in response to said operation mode detecting means, and facilitating means (W11, W12, W21, W22) for facilitating the determination of the first logic of the second state control signal more than the determination of the first logic of the first state control signal by controlling the threshold levels of said first and second determining means.
Claim 3
Dependent Claim
66 words
The semiconductor memory according to claim 1, wherein said first determining means includes first inverter means (22a) connected to receive said first state control signal, said second determining means includes second inverter means (21a) connected to receive said second state control signal, said facilitating means includes threshold voltage controlling means (W11, W12, W21, W22) for controlling the threshold voltages of said first and second inverter means.
Claim 4
Dependent Claim
107 words
The semiconductor memory according to claim 2, wherein said first inverter means includes a first field effect transistor (Q21) of a conductive type and a second field effect transistor (Q22) of the opposite conductive type connected in series between first and second power supply potentials, said second inverter means includes a third field effect transistor (Q11) of a conductive type and a fourth field effect transistor (Q12) of the opposite conductive type connected in series between the first and the second power supply potentials, said threshold voltage controlling means includes means (W11, W12, W21, W22) for controlling channel widths of said first to fourth field effect transistors.
Claim 5
Dependent Claim
51 words
The semiconductor memory according to claim 1, wherein said predetermined operation mode includes a test mode for testing said semiconductor memory, said operation mode detecting means includes test mode controller means (14) responsive to said first and second determining means for causing said semiconductor memory to operate under the test mode.
Claim 6
Dependent Claim
50 words
The semiconductor memory according to claim 1, wherein said first state control signal includes a column address strobe signal (CAS), said second state control signal includes a row address strobe signal (RAS), said first logic is defined by a L level, said second logic is defined by a H level.
Claim 7
Dependent Claim
18 words
The semiconductor memory according to claim 1, wherein said semiconductor memory includes a dynamic random access memory (DRAM).
Claim 8
Dependent Claim
162 words
A dynamic random access memory (DRAM) operable under a predetermined test mode designated by a combination of externally applied external RAS signal and external CAS signal, comprising, an RAS input circuit (100a) for receiving the external RAS signal to generate an internal RAS signal determined by a first predetermined threshold voltage; a CAS input circuit (200a) for receiving the external CAS signal to generate an internal CAS signal determined by a second predetermined threshold voltage; a test mode detecting circuit (14) for detecting a designation of the test mode in response to the internal RAS signal changing from a H level to a L level while the internal CAS signal is at a L level; said semiconductor memory starting its operation under the test mode in response to said test mode detecting circuit, and means (W11, W12, W21, W22) for setting the threshold voltage of said RAS input circuit to a level higher than the threshold voltage of said CAS input circuit.
Claim 9
Dependent Claim
162 words
A dynamic random access memory (DRAM) operable under a predetermined test mode designated by a combination of externally applied external RAS signal and external CAS signal, comprising, an RAS input circuit (100a) for receiving the external RAS signal to generate an internal RAS signal determined by a first predetermined threshold voltage; a CAS input circuit (200a) for receiving the external CAS signal to generate an internal CAS signal determined by a second predetermined threshold voltage; a test mode detecting circuit (14) for detecting a designation of the test mode in response to the internal RAS signal changing from a H level to a L level while the internal CAS signal is at a L level; said semiconductor memory starting its operation under the test mode in response to said test mode detecting circuit, and means (W11, W12, W21, W22) for setting the threshold voltage of said RAS input circuit to a level higher than the threshold voltage of said CAS input circuit.
References Cited (Backward Citations)
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Cited
US5088063A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-10-20 | 1996-04-20 | 1996-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-10-20 | 2000-04-20 | 2000-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-10-20 | 2004-04-20 | 2004-10-20 | $7700.00 | Window Closed / Lapsed |