CMOS power-on reset circuit

Claim 2

A circuit responsive to an increasing potential supplied at a first power supply conductor for providing at an output an output signal indicative of the increasing potential until reaching a predetermined threshold of the increasing potential whereat the output signal is substantially reduced, comprising: first means coupled to the first power supply conductor for providing the output signal which tracks the increasing potential of the first power supply conductor; second means responsive to the increasing potential of the first power supply conductor upon detecting the predetermined threshold thereof for inhibiting said first means such that the output signal is substantially reduced; and third means responsive to the reduced output signal for suppressing the current flowing through first and second means.

Claim 3

The circuit of claim 1 wherein said second means comprises: a first transistor having a gate, a drain and a source, said gate being coupled to the first power supply conductor, said source being coupled to a second power supply conductor; at least one diode means serially coupled between the first power supply conductor and said drain of said first transistor; and a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said source being coupled to said second power supply conductor, said drain being coupled to the output.

Claim 4

The circuit of claim 2 wherein said first means comprises a third transistor having a gate, a drain and a source, said gate being coupled to said second power supply conductor, said drain being coupled to said drain of said second transistor, said source being coupled to the first power supply conductor.

Claim 5

The circuit of claim 3 wherein said third means comprises a fourth transistor having a gate, a drain and a source, said drain being coupled to said source of said third transistor, said source being coupled to the first power supply conductor.

Claim 6

The circuit of claim 4 wherein said third means further comprises a fifth transistor having a gate, a drain and a source, said gate being coupled to the output, said drain being coupled to said source of said first transistor, said source being coupled to said second power supply conductor.

Claim 7

The circuit of claim 5 wherein said first means further comprises a driver circuit coupled between said drain of said second transistor and the output.

Claim 8

The circuit of claim 6 wherein said driver circuit comprises a first inverter having an input coupled to said drain of said second transistor and having an output.

Claim 9

The circuit of claim 7 wherein said driver circuit further comprises a second inverter having an input coupled to said output of said first inverter and having an output coupled to the output.

Claim 10

The circuit of claim 8 wherein said first inverter comprises: a sixth transistor having a gate, a drain and a source, said gate being coupled to said input of said first inverter, said drain being coupled to said output of said first inverter, said source being coupled to the first power supply conductor; and a seventh transistor having a gate, a drain and a source, said gate being coupled to said input of said first inverter, said drain being coupled to said output of said first inverter, said source being coupled to said second power supply conductor.

Claim 11

The circuit of claim 9 wherein said second inverter comprises: an eighth transistor having a gate, a drain and a source, said gate being coupled to said input of said second inverter, said drain being coupled to said output of said second inverter, said source being coupled to the first power supply conductor; and a ninth transistor having a gate, a drain and a source, said gate being coupled to said input of said second inverter, said drain being coupled to said output of said second inverter, said source being coupled to said second power supply conductor.

Claim 12

A circuit having an output for providing an output signal in response to the power-on transient of a first power supply conductor wherein the output signal changes state at a predetermined threshold of the potential developed at the first power supply conductor independent of the slew rate thereof, comprising: a first transistor having a drain, a source and a gate coupled to the first power supply conductor; at least one diode means serially coupled between the first power supply conductor and said drain of said first transistor; a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said source being coupled to a second power supply conductor, said drain being coupled to the output; a third transistor having a gate, a drain and a source, said gate being coupled to said second power supply conductor, said drain being coupled to said drain of said second transistor; a fourth transistor having a gate, a drain and a source, said drain being coupled to said source of said third transistor, said source being coupled to the first power supply conductor; and a fifth transistor having a gate, a drain and a source, said gate being coupled to the output, said drain being coupled to said source of said first transistor, said source being coupled to said second power supply conductor.

Claim 13

A circuit having an output for providing an output signal in response to the power-on transient of a first power supply conductor wherein the output signal changes state at a predetermined threshold of the potential developed at the first power supply conductor independent of the slew rate thereof, comprising: a first transistor having a drain, a source and a gate coupled to the first power supply conductor; at least one diode means serially coupled between the first power supply conductor and said drain of said first transistor; a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said source being coupled to a second power supply conductor, said drain being coupled to the output; a third transistor having a gate, a drain and a source, said gate being coupled to said second power supply conductor, said drain being coupled to said drain of said second transistor; a fourth transistor having a gate, a drain and a source, said drain being coupled to said source of said third transistor, said source being coupled to the first power supply conductor; and a fifth transistor having a gate, a drain and a source, said gate being coupled to the output, said drain being coupled to said source of said first transistor, said source being coupled to said second power supply conductor.

Claim 14

The circuit of claim 11 further comprising a driver circuit coupled between said drain of said second transistor and the output.

Claim 15

The circuit of claim 12 wherein said driver circuit comprises a first inverter having an input coupled to said drain of said second transistor and having an output.

Claim 16

The circuit of claim 13 wherein said driver circuit further comprises a second inverter having an input coupled to said output of said first inverter and having an output coupled to the output.

Claim 17

The circuit of claim 14 wherein said first inverter comprises: a sixth transistor having a gate, a drain and a source, said gate being coupled to said input of said first inverter, said drain being coupled to said output of said first inverter, said source being coupled to the first power supply conductor; and a seventh transistor having a gate, a drain and a source, said gate being coupled to said input of said first inverter, said drain being coupled to said output of said first inverter, said source being coupled to said second power supply conductor.

Claim 18

The circuit of claim 15 wherein said second inverter comprises: an eighth transistor having a gate, a drain and a source, said gate being coupled to said input of said second inverter, said drain being coupled to said output of said second inverter, said source being coupled to the first power supplu conductor; and an ninth transistor having a gate, a drain and a source, said gate being coupled to said input of said second inverter, said drain being coupled to said output of said second inverter, said source being coupled to said second power supply conductor.

Claim 19

An integrated circuit having an output for providing an output signal in response to the power-on transient of a first power supply conductor wherein the output signal changes state at a predetermined threshold of the potential developed at the first power supply conductor independent of the slew rate thereof, comprising: a first transistor having a drain, a source and a gate coupled to the first power supply conductor; at least one diode means serially coupled between the first power supply conductor and said drain of said first transistor; a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said source being coupled to a second power supply conductor, said drain being coupled to the output; a third transistor having a gate, a drain and a source, said gate being coupled to said second power supply conductor, said drain being coupled to said drain of said second transistor; a fourth transistor having a gate, a drain and a source, said drain being coupled to said source of said third transistor, said source being coupled to the first power supply conductor; and a fifth transistor having a gate, a drain and a source, said gate being coupled to the output, said drain being coupled to said source of said first transistor, said source being coupled to said second power supply conductor.

Claim 20

An integrated circuit having an output for providing an output signal in response to the power-on transient of a first power supply conductor wherein the output signal changes state at a predetermined threshold of the potential developed at the first power supply conductor independent of the slew rate thereof, comprising: a first transistor having a drain, a source and a gate coupled to the first power supply conductor; at least one diode means serially coupled between the first power supply conductor and said drain of said first transistor; a second transistor having a gate, a drain and a source, said gate being coupled to said drain of said first transistor, said source being coupled to a second power supply conductor, said drain being coupled to the output; a third transistor having a gate, a drain and a source, said gate being coupled to said second power supply conductor, said drain being coupled to said drain of said second transistor; a fourth transistor having a gate, a drain and a source, said drain being coupled to said source of said third transistor, said source being coupled to the first power supply conductor; and a fifth transistor having a gate, a drain and a source, said gate being coupled to the output, said drain being coupled to said source of said first transistor, said source being coupled to said second power supply conductor.