US5027008A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS clamp circuits
Assignee: Advanced Micro Devices Inc
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Filing: 1990-02-15
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Granted: 1991-06-25
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Expires: 2010-02-15
Abstract
Abstract A CMOS clamp circuit (28) includes a sense inverter (I5) having an input node for receiving a sense current signal and an output node for generating a voltage output, an N-channel MOS clamping transistor (N5), and a P-channel MOS clamping transistor (P5). The N-channel clamping transistor (N5) has its drain connected to an upper power supply potential (VCC) and its source connected to the input node of the inverter (I5). The P-channel clamping transistor (P5) has its drain connected to a lower power supply potential (VSS) and its source connected to the input node of the sense inverter (I5). The gates of the N-channel and P-channel transistors (N5, P5) are connected to the output node of the sense inverter (I5). An enabling transistor and a power-down transistor may also be provided so as to operate the clamp circuit in a power-down mode of operation. <IMAGE>
Inventors
- 👤 Thomas J. Runaldue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/0008; H03K19/0016; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K5/00; H03K5/01; H03K5/08
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
132 words
A CMOS clamping circuit comprising: sense inverter means (I6) having an input node for receiving a sense current signal and an output node for generating a voltage output; an N-channel MOS clamping transistor (N6) having its gate connected to the output node of said inverter means and it source connected to the input node of said inverter means; a P-channel MOS clamping transistor (P6) having its gate connected to the output of said inverter means, its source connected to the input node of said inverter means, and its drain connected to a lower power supply potential (VSS); and enabling means responsive to a complementary activate clamp signal for deactivating said N-channel clamping transistor (N6) so as to reduce power consumption when the output node of said inverter means is not being used.
Claim 2
Dependent Claim
132 words
A CMOS clamping circuit comprising: sense inverter means (I6) having an input node for receiving a sense current signal and an output node for generating a voltage output; an N-channel MOS clamping transistor (N6) having its gate connected to the output node of said inverter means and it source connected to the input node of said inverter means; a P-channel MOS clamping transistor (P6) having its gate connected to the output of said inverter means, its source connected to the input node of said inverter means, and its drain connected to a lower power supply potential (VSS); and enabling means responsive to a complementary activate clamp signal for deactivating said N-channel clamping transistor (N6) so as to reduce power consumption when the output node of said inverter means is not being used.
Claim 3
Dependent Claim
65 words
A CMOS clamping circuit as claimed in claim 1, wherein said enabling means comprises a P-channel MOS enabling transistor (P7) having its source connected to an upper power supply potential (VCC) and its drain connected to the drain of said N-channel clamping transistor (N6), the gate of said enabling transistor (P7) being connected to a second input node for receiving the complementary activate clamp signal.
Claim 4
Dependent Claim
48 words
A CMOS clamp circuit as claimed in claim 2, further comprising power-down means responsive to the complementary activate clamp signal for pulling down the input node of said inverter means to the lower power supply potential (VSS) so as to have no current flow in said inverter means.
Claim 5
Dependent Claim
58 words
A CMOS clamp circuit as claimed in claim 3, wherein said power-down means comprises an N-channel MOS pull-down transistor (N7) having its drain connected to the input node of said inverter means, its source connected to the lower power supply potential (VSS), and its gate connected to the second input node for receiving the complementary activate clamp signal.
Claim 6
Dependent Claim
58 words
A CMOS clamp circuit as claimed in claim 4, wherein said inverter means comprises a CMOS inverter formed of a P-channel MOS transistor and an N-channel MOS transistor, the gates of said P-channel and N-channel transistors being connected together defining the input node, the drains of said P-channel and N-channel transistors being connected together defining the output node.
Claim 7
Dependent Claim
37 words
A CMOS clamp circuit as claimed in claim 5, wherein said enabling transistor (P7) is turned off and said pull-down transistor (N7) is turned on when said complementary activate clamp signal is at a high logic level.
Claim 8
Dependent Claim
132 words
A CMOS clamping circuit comprising: sense inverter means (I7) having an input node for receiving a sense current signal and an output node for generating a voltage output; a P-channel MOS clamping transistor (P8) having its gate connected to the output node of said inverter means and it source connected to the input node of said inverter means; an N-channel MOS clamping transistor (N8) having its gate connected to the output of said inverter means, its source connected to the input node of said inverter means, and its drain connected to an upper power supply potential (VCC); and enabling means responsive to a true activate clamp signal for deactivating said P-channel clamping transistor (P8) so as to reduce power consumption when the output node of said inverter means is not being used.
Claim 9
Dependent Claim
132 words
A CMOS clamping circuit comprising: sense inverter means (I7) having an input node for receiving a sense current signal and an output node for generating a voltage output; a P-channel MOS clamping transistor (P8) having its gate connected to the output node of said inverter means and it source connected to the input node of said inverter means; an N-channel MOS clamping transistor (N8) having its gate connected to the output of said inverter means, its source connected to the input node of said inverter means, and its drain connected to an upper power supply potential (VCC); and enabling means responsive to a true activate clamp signal for deactivating said P-channel clamping transistor (P8) so as to reduce power consumption when the output node of said inverter means is not being used.
Claim 10
Dependent Claim
65 words
A CMOS clamping circuit as claimed in claim 7, wherein said enabling means comprises an N-channel MOS enabling transistor (N9) having its source connected to a lower power supply potential (VSS) and its drain connected to the drain of said P-channel clamping transistor (P8), the gate of said enabling transistor (N9) being connected to a second input node for receiving the true activate clamp signal.
Claim 11
Dependent Claim
48 words
A CMOS clamp circuit as claimed in claim 8, further comprising power-down means responsive to the true activate clamp signal for pulling up the input node of said inverter means to the upper power supply potential (VCC) so as to have no current flow in said inverter means.
Claim 12
Dependent Claim
58 words
A CMOS clamp circuit as claimed in claim 9, wherein said power-down means comprises a P-channel MOS pull-up transistor (P9) having its drain connected to the input node of said inverter means, its source connected to the upper power supply potential (VCC), and its gate connected to the second input node for receiving the true activate clamp signal.
Claim 13
Dependent Claim
58 words
A CMOS clamp circuit as claimed in claim 10, wherein said inverter means comprises a CMOS inverter formed of a P-channel MOS transistor and an N-channel MOS transistor, the gates of said P-channel and N-channel transistors being connected together defining the input node, the drains of said P-channel and N-channel transistors being connected together defining the output node.
Claim 14
Dependent Claim
37 words
A CMOS clamp circuit as claimed in claim 11, wherein said enabling transistor (N9) is turned off and said pull-up transistor (P9) is turned on when said true activate clamp signal is at a low logic level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-24 | 1994-12-24 | 1995-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-24 | 1998-12-24 | 1999-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-24 | 2002-12-24 | 2003-06-25 | $7700.00 | Window Closed / Lapsed |