Sense amplifier providing a rapid output transition

Claim 2

A sense circuitry operable to detect the logic state of a sense node coupled to a plurality of programmable switches selectively enabled by respective input signals, comprising: first voltage control circuitry for selectively coupling the sense node to a first voltage source responsive to a first control signal; feedback circuitry for generating said first control signal such that said first voltage control circuitry decouples the sense node from said first voltage source responsive to said sense node reaching a predetermined voltage; and second voltage control circuitry to maintain said predetermined voltage on said source node until one of said programmable switches is enabled wherein said second voltage control circuitry comprises a first N-channel FET, having a gate and a source and a drain disposed in a P-well, and a second N-channel FET, having a gate and a source and a drain disposed in a P-well.

Claim 3

The sense circuitry of claim 1 wherein said first voltage control circuitry comprises a first P-channel transistor having a gate connected to said feedback circuitry, a first source/drain connected to said voltage source and a second source/drain connected to said sense node.

Claim 4

The sense circuitry of claim 1 wherein said feedback circuitry comprises two inverters.

Claim 5

The sense circuitry of claim 2 wherein said feedback circuitry comprises a first inverter having an input coupled to the sense node and said second inverter having an input connected to the output of said first inverter.

Claim 6

The sense circuitry of claim 4 wherein said first and second inverters have trip points such that said first P-channel transistor is disabled responsive to said predetermined voltage.

Claim 7

The sense circuitry of claim 1 wherein the gate and first source/drain region of said first N-channel transistor is coupled to said first voltage source, the second source/drain of the first N-channel transistor is coupled to the gate and the first source/drain of the second N-channel transistor, and the second source/drain of the second N-channel transistor is coupled to the sense node.

Claim 8

The sense circuitry of claim 1 and further comprising an inverter coupled to said sense node.

Claim 9

The sense circuitry of claim 1 wherein said programmable switches comprise non-volatile memory cells.

Claim 10

The sense circuitry of claim 8 wherein said non-volatile memory cells comprise FAMOS transistors.

Claim 11

The sense circuitry of claim 1 and further comprising zero power circuitry operable to disable said first and said second voltage control circuitry responsive to a second control signal.

Claim 12

The sense circuitry of claim 10 wherein said zero power circuitry comprises: a second P-channel FET, having a gate operable to receive said second control signal, a source coupled to said first voltage source and a drain coupled to said first voltage control circuitry; and a third N-channel FET, having a gate coupled to said gate of said second P-channel FET, a source coupled to a second voltage source and a drain coupled to said sense node.

Claim 13

A circuit for providing a rapid output transition responsive to an input transition, comprising: a sense node; a floating-gate MOS memory cell coupled to said sense node and operable to selectively couple said sense node to a first voltage source when in a first state and decouple said sense node from said first voltage source when in a second state; current generating circuitry coupled to said sense node and operable to increase the speed of said sense node transition from a low logic state to a high logic state; switching circuitry coupled between said sense node and said current generating circuitry responsive to the state of said memory cell and operable to enable and disable said current generating circuitry; and voltage generating circuitry coupled to said sense node responsive to said memory cell output and operable to maintain said sense node in a high logic state while said current generating circuitry is disabled wherein said voltage generating circuitry comprises a first N-channel FET, having a gate and a source and a drain disposed in a P-well, and a second N-channel FET, having a gate and a source and a drain disposed in a P-well.

Claim 14

A circuit for providing a rapid output transition responsive to an input transition, comprising: a sense node; a floating-gate MOS memory cell coupled to said sense node and operable to selectively couple said sense node to a first voltage source when in a first state and decouple said sense node from said first voltage source when in a second state; current generating circuitry coupled to said sense node and operable to increase the speed of said sense node transition from a low logic state to a high logic state; switching circuitry coupled between said sense node and said current generating circuitry responsive to the state of said memory cell and operable to enable and disable said current generating circuitry; and voltage generating circuitry coupled to said sense node responsive to said memory cell output and operable to maintain said sense node in a high logic state while said current generating circuitry is disabled wherein said voltage generating circuitry comprises a first N-channel FET, having a gate and a source and a drain disposed in a P-well, and a second N-channel FET, having a gate and a source and a drain disposed in a P-well.

Claim 15

The circuit of claim 12 and further comprising inverter circuitry having an input coupled to said sense node and operable to invert the logic state of said sense node.

Claim 16

The circuit of claim 12 wherein said current generating circuitry comprises a first P-channel FET having a gate, a source and a drain.

Claim 17

The circuit of claim 14 wherein said gate is coupled to said switching circuitry, said source is coupled to said sense node and said drain is coupled to voltage source V cc .

Claim 18

The circuit of claim 12 wherein said switching circuitry comprises a first inverter circuitry having a first input and a first output and a second inverter circuitry having a second input and a second output.

Claim 19

The circuit of claim 16 wherein said first input is coupled to said sense node, said first output is coupled to said second input, and said second output is coupled to said gate of said P-channel FET.

Claim 20

The circuit of claim 12 wherein said gate of said first FET is coupled to V cc , said drain of said first FET is coupled to V cc , said P-well of said first FET is coupled to said first voltage source, said source of said first FET is coupled to said gate of said second FET, said drain of said second FET is coupled to said gate of said second FET, said P-well of said second FET is coupled to said first voltage source, and said source of said second FET is coupled to said sense node.

Claim 21

The circuit of claim 12 and further comprising zero power circuitry operable to disable said current generating circuitry and said voltage generating circuitry responsive to a control signal.

Claim 22

The circuit of claim 19 wherein said zero power circuitry comprises: a second P-channel FET, having a gate operable to receive said control signal, a source coupled to a first voltage source and a drain coupled to said current generating circuitry; and a third N-channel FET, having a gate coupled to said gate of said second P-channel FET, a source coupled to a second voltage source and a drain coupled to said sense node.

Claim 23

Programmable array logic comprising: a plurality of inputs; a plurality of product lines; a plurality of programmable switching devices selectively coupling each product line to a first voltage source responsive to an associated input; and sensing circuitry associated with each product line, comprising: first voltage control circuitry for selectively coupling the product line to a second voltage source responsive to a first control signal; feedback circuitry for generating said first control signal responsive to the voltage on the associated product line; and second voltage control circuitry to maintain a predetermined voltage on said product line when said product line is not coupled to said first voltage source wherein said second voltage control circuitry comprises a first N-channel FET, having a gate and a source and a drain disposed in a P-well, and a second N-channel FET, having a gate and a source and a drain disposed in a P-well.

Claim 24

Programmable array logic comprising: a plurality of inputs; a plurality of product lines; a plurality of programmable switching devices selectively coupling each product line to a first voltage source responsive to an associated input; and sensing circuitry associated with each product line, comprising: first voltage control circuitry for selectively coupling the product line to a second voltage source responsive to a first control signal; feedback circuitry for generating said first control signal responsive to the voltage on the associated product line; and second voltage control circuitry to maintain a predetermined voltage on said product line when said product line is not coupled to said first voltage source wherein said second voltage control circuitry comprises a first N-channel FET, having a gate and a source and a drain disposed in a P-well, and a second N-channel FET, having a gate and a source and a drain disposed in a P-well.

Claim 25

The programmable array logic of claim 21 wherein said first voltage source is at ground voltage.

Claim 26

The programmable array logic of claim 21 wherein said second voltage source is at V cc .

Claim 27

The programmable array logic of claim 21 wherein said first voltage control circuitry comprises a first P-channel transistor having a gate connected to said feedback circuitry, a first source/drain connected to said second voltage source and a second source/drain connected to said product line.

Claim 28

The programmable array logic of claim 24 wherein said feedback circuitry comprises a first and second inverters, each inverter having an input and an output, the input of said first inverter connected to said product line, the output of said first inverter connected to the input of said second inverter and the output of said second inverter connected to the gate of said P-channel transistor.

Claim 29

The programmable array logic of claim 21 wherein said programmable switching devices comprise non-volatile memory cells.

Claim 30

The programmable array logic of claim 26 wherein said non-volatile memory cells comprise FAMOS transistors.

Claim 31

The programmable array logic of claim 21 and further comprising zero power circuitry operable to disable said first and said second voltage control circuitry responsive to a second control signal.

Claim 32

The programmable array logic of claim 28 wherein said zero power circuitry comprises: a second P-channel FET, having a gate operable to receive said second control signal, a source coupled to said second voltage source and a drain coupled to said first voltage control circuitry; and a third N-channel FET, having a gate coupled to said gate of said second P-channel FET, a source coupled to said first voltage source and a drain coupled to said product lines.

Claim 35

The method of claim 30 wherein said step of providing current to said product line comprises the step of enabling a P-channel FET current source coupled to said product line.

Claim 36

The method of claim 31 wherein said step of disabling said current provision comprises the step of turning off said P-channel FET current source.

Claim 37

The method of claim 32 wherein said step of maintaining the voltage on the product line comprises the step generating a predetermined voltage across two N-channel FETs coupled between said product line and a voltage source.

Claim 38

The method of claim 30, further comprising the step of disabling said current provision and said voltage generation responsive to a control signal.

Claim 39

A sense circuitry operable to detect the logic state of a sense node coupled to a plurality of programmable switches selectively enabled by respective input signals, comprising: first voltage control circuitry for selectively coupling the sense node to a first voltage source responsive to a first control signal; feedback circuitry for generating said first control signal such that said first voltage control circuitry decouples the sense node from said first voltage source responsive to said sense node reaching a predetermined voltage; second voltage control circuitry to maintain said predetermined voltage on said source node until one of said programmable switches is enabled; and zero power circuitry operable to disable said first and said second voltage control circuitry responsive to a second control signal.

Claim 40

A sense circuitry operable to detect the logic state of a sense node coupled to a plurality of programmable switches selectively enabled by respective input signals, comprising: first voltage control circuitry for selectively coupling the sense node to a first voltage source responsive to a first control signal; feedback circuitry for generating said first control signal such that said first voltage control circuitry decouples the sense node from said first voltage source responsive to said sense node reaching a predetermined voltage; second voltage control circuitry to maintain said predetermined voltage on said source node until one of said programmable switches is enabled; and zero power circuitry operable to disable said first and said second voltage control circuitry responsive to a second control signal.

Claim 41

A circuit for providing a rapid output transition responsive to an input transition, comprising: a sense node; a floating-gate MOS memory cell coupled to said sense node and operable to selectively couple said sense node to a first voltage source when in a first state and decouple said sense node from said first voltage source when in a second state; current generating circuitry coupled to said sense node and operable to increase the speed of said sense node transition from a low logic state to a high logic state; switching circuitry coupled between said sense node and said current generating circuitry responsive to the state of said memory cell and operable to enable and disable said current generating circuitry; voltage generating circuitry coupled to said sense node responsive to said memory cell output and operable to maintain said sense node in a high logic state while said current generating circuitry is disabled; and zero power circuitry operable to disable said current generating circuitry and said voltage generating circuitry responsive to a first control signal.

Claim 42

A circuit for providing a rapid output transition responsive to an input transition, comprising: a sense node; a floating-gate MOS memory cell coupled to said sense node and operable to selectively couple said sense node to a first voltage source when in a first state and decouple said sense node from said first voltage source when in a second state; current generating circuitry coupled to said sense node and operable to increase the speed of said sense node transition from a low logic state to a high logic state; switching circuitry coupled between said sense node and said current generating circuitry responsive to the state of said memory cell and operable to enable and disable said current generating circuitry; voltage generating circuitry coupled to said sense node responsive to said memory cell output and operable to maintain said sense node in a high logic state while said current generating circuitry is disabled; and zero power circuitry operable to disable said current generating circuitry and said voltage generating circuitry responsive to a first control signal.

Claim 43

Programmable array logic comprising: a plurality of inputs; a plurality of product lines; a plurality of programmable switching devices selectively coupling each product line to a first voltage source responsive to an associated input; and sensing circuitry associated with each product line, comprising: first voltage control circuitry for selectively coupling the product line to a second voltage source responsive to a first control signal; feedback circuitry for generating said control signal responsive to the voltage on the associated product line; second voltage control circuitry to maintain a predetermined voltage on said product line when said product line is not coupled to said first voltage source; and zero power circuitry operable to disable said first and said second voltage control circuitry responsive to a second control signal.

Claim 44

Programmable array logic comprising: a plurality of inputs; a plurality of product lines; a plurality of programmable switching devices selectively coupling each product line to a first voltage source responsive to an associated input; and sensing circuitry associated with each product line, comprising: first voltage control circuitry for selectively coupling the product line to a second voltage source responsive to a first control signal; feedback circuitry for generating said control signal responsive to the voltage on the associated product line; second voltage control circuitry to maintain a predetermined voltage on said product line when said product line is not coupled to said first voltage source; and zero power circuitry operable to disable said first and said second voltage control circuitry responsive to a second control signal.