Static PLA or ROM circuit with self-generated precharge

Claim 2

A static PLA circuit comprising: a NOR logic gate having inputs for receiving input select signals and having an output; a precharge MOS transistor having one of its main electrodes connected to a supply potential and its other main electrode connected to the output of said NOR gate; said percharge MOS transistor being formed of an N-channel transistor; a feedback circuit portion formed of inverter means connected between the output of said NOR gate and the gate of said precharge MOS transistor; and said inverter means including a first inverter, a second inverter and a third inverter, said first inverter having its input connected to the output of said NUR gate and its output connected to the input of said second inverter, said third inverter having its input connected to the output of said second inverter and its output connected to the gate of said N-channel transistor.

Claim 3

A static PLA circuit as claimed in claim 1, further comprising a resistor having its one end connected to the supply potential and its other end connected to the output of said NOR gate.

Claim 4

A static PLA circuit as claimed in claim 1, wherein said N-channel transistor is delayed in its turn-on time by said first, second and third inverters when the output of said NOR gate is making a high-to-low transition.

Claim 5

A static PLA circuit comprising: logic gate means having inputs for receiving input select signals and an output; a precharge MOS transistor having one of its main electrodes connected to a supply potential and its other main electrode connected to the output of said logic gate means; and feedback means connected between the output of said logic gate means and the gate of said precharge MOS transistor for delaying the turn-on time of said MOS transistor when the output of said logic gate means is making a high-to-low transition in response to said input select signals and for delaying the turn-off time of said MOS transistor when the output of said logic gate means is making a low-to-high transition in response to said input select signals.

Claim 6

A static PLA circuit comprising: logic gate means having inputs for receiving input select signals and an output; a precharge MOS transistor having one of its main electrodes connected to a supply potential and its other main electrode connected to the output of said logic gate means; and feedback means connected between the output of said logic gate means and the gate of said precharge MOS transistor for delaying the turn-on time of said MOS transistor when the output of said logic gate means is making a high-to-low transition in response to said input select signals and for delaying the turn-off time of said MOS transistor when the output of said logic gate means is making a low-to-high transition in response to said input select signals.

Claim 7

A static PLA circuit as claimed in claim 4, wherein said precharge MOS transistor comprises a p-channel transistor.

Claim 8

A static PLA circuit as claimed in claim 4, wherein said precharge MOS transistor comprises an N-channel transistor.

Claim 9

A static PLA circuit as claimed in claim 5, wherein said feedback means includes a first inverter and a second inverter, said first inverter having its input connected to the output of said NOR gate and it output connected to the input of said second inverter, said second inverter having its output connected to the gate of said P-channel transistor.

Claim 10

A static PLA circuit as claimed in claim 6, wherein said feedback means includes a first inverter, a second inverter and a third inverter, said first inverter having its input connected to the output of said NOR gate and its output connected to the input of said second inverter, said third inverter having its input connected to the output of said second inverter and its output connected to the gate of said N-channel transistor.

Claim 11

A static PLA circuit as claimed in claim 7, further comprising a resistor having its one end connected to the supply potential and its other end connected to the output of said NOR gate.

Claim 12

A static PLA circuit as claimed in claim 8, further comprising a resistor having its one end connected to the supply potential and its other end connected to the output of said NOR gate.

Claim 13

A static PLA circuit as claimed in claim 4, wherein said logic gate means comprises a NOR gate.

Claim 14

A static PLA circuit as claimed in claim 11, wherein said NOR gate is formed of at least two N-channel MOS transistors, said N-channel transistors having their drains connected together to form the output of said logic gate means, said N-channel transistors having their sources connected together and to a ground potential, said N-channel transistors having their gates connected to respective ones of said input select signals.

Claim 15

A static PLA circuit comprising: a NOR logic gate having inputs for receiving input select signals and having an output; a precharge MOS transistor having one of its main electrodes connected to a supply potential and its other main electrode connected to the output of said NOR gate; said precharge MOS transistor being formed of a P-channel transistor; a feedback circuit portion formed of inverter means connected between the output of said NOR gate and the gate of said precharge MOS transistor; said inverter means including a first inverter and a second inverter, said first inverter having its input connected to the output of said NOR gate and its output connected to the input of said second inverter, said second inverter having its output connected to the gate of said P-channel transistor; and said P-channel transistor being delayed in its turn-on time by said first and second inverters when the output of said NOR gate is making a high-to-low transition.

Claim 16

A static PLA circuit comprising: a NOR logic gate having inputs for receiving input select signals and having an output; a precharge MOS transistor having one of its main electrodes connected to a supply potential and its other main electrode connected to the output of said NOR gate; said precharge MOS transistor being formed of a P-channel transistor; a feedback circuit portion formed of inverter means connected between the output of said NOR gate and the gate of said precharge MOS transistor; said inverter means including a first inverter and a second inverter, said first inverter having its input connected to the output of said NOR gate and its output connected to the input of said second inverter, said second inverter having its output connected to the gate of said P-channel transistor; and said P-channel transistor being delayed in its turn-on time by said first and second inverters when the output of said NOR gate is making a high-to-low transition.

Claim 17

A static PLA circuit as claimed in claim 13, further comprising a resistor having its one end connected to the supply potential and its other end connected to the output of said NOR gate.