US4645952A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed NOR gate
Assignee: STMicroelectronics lnc USA
•
Filing: 1985-11-14
•
Granted: 1987-02-24
•
Expires: 2005-11-14
Abstract
Abstract A high speed CMOS NOR gate employs a pair of cross-coupled inverters and a dual set of N-channel pulldown transistors (202, 203) at each of the nodes between the two inverters, together with small pullup transistor (205) on the output terminal that is permanently energized and a switchable large pullup transistor (220) that is a link between the second inverter output and the first inverter input.
Inventors
- 👤 Hiep Van Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:10
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
462 words
A NOR gate comprising at least two input terminals, a first group of transistors of predetermined type, each having a first current capacity, and a second group of transistors, each having a second current capacity, in which; each of said at least two input terminals is connected to one of the gates of the transistors of said first group and also to one of the gates of the transistors of the second group; said first group of transistors is connected in parallel between an output node; and a first current supply terminal; and said output node has pulling means, having a predetermined pulling means current capacity connected thereto, for maintaining said output node in a default voltage state; said second group of transistors, having said predetermined type, are connected in parallel between an intermediate node and said first current supply terminal; a first inverter, having a first inverter trip point, is connected between said output node and said intermediate node, with a first inverter input connected to said output node and a first inverter output connected to said intermediate node said first inverter having a first inverter pulling current capacity at its output; a second inverter, having a second inverter trip point, a second inverter input and a second inverter output, has said second inverter input connected to said intermediate node; a pulling transistor, having a pulling current capacity, is connected between a second current supply terminal and said output node, with a pulling gate connected to said second inverter output, said first current capacity, second current capacity, pulling means current capcity and first inverter pulling current capacity being related to one another and to said first and second inverter trip points by the conditions that: said first current capacity is sufficiently greater than said pulling means current capacity that, when both said pulling means and one of said first group of transistors are conductive, the voltage on said output node is closer to the voltage of said first current supply terminal, and larger than the voltage at which the firt inverter trip point occurs; and said second current capacity is sufficiently greter than said first inverter pulling capacity that, when one of said second group of transistors and said first inverter are pulling toward opposite current terminals, the voltage on said intermediate node is closer to the voltage of said first current supply terminal than the voltage at which said second trip point occur, whereby, when a signal on one of said at least two input terminals activates one transistor of each of said first and second groups of transistors, said output node switches from said default voltage state to an opposite voltage state and both of said first and second inverters remain in a first and second normal inverter state.
Claim 2
Dependent Claim
462 words
A NOR gate comprising at least two input terminals, a first group of transistors of predetermined type, each having a first current capacity, and a second group of transistors, each having a second current capacity, in which; each of said at least two input terminals is connected to one of the gates of the transistors of said first group and also to one of the gates of the transistors of the second group; said first group of transistors is connected in parallel between an output node; and a first current supply terminal; and said output node has pulling means, having a predetermined pulling means current capacity connected thereto, for maintaining said output node in a default voltage state; said second group of transistors, having said predetermined type, are connected in parallel between an intermediate node and said first current supply terminal; a first inverter, having a first inverter trip point, is connected between said output node and said intermediate node, with a first inverter input connected to said output node and a first inverter output connected to said intermediate node said first inverter having a first inverter pulling current capacity at its output; a second inverter, having a second inverter trip point, a second inverter input and a second inverter output, has said second inverter input connected to said intermediate node; a pulling transistor, having a pulling current capacity, is connected between a second current supply terminal and said output node, with a pulling gate connected to said second inverter output, said first current capacity, second current capacity, pulling means current capcity and first inverter pulling current capacity being related to one another and to said first and second inverter trip points by the conditions that: said first current capacity is sufficiently greater than said pulling means current capacity that, when both said pulling means and one of said first group of transistors are conductive, the voltage on said output node is closer to the voltage of said first current supply terminal, and larger than the voltage at which the firt inverter trip point occurs; and said second current capacity is sufficiently greter than said first inverter pulling capacity that, when one of said second group of transistors and said first inverter are pulling toward opposite current terminals, the voltage on said intermediate node is closer to the voltage of said first current supply terminal than the voltage at which said second trip point occur, whereby, when a signal on one of said at least two input terminals activates one transistor of each of said first and second groups of transistors, said output node switches from said default voltage state to an opposite voltage state and both of said first and second inverters remain in a first and second normal inverter state.
Claim 3
Dependent Claim
44 words
A NOR gate according to claim 1, in which said predetermined type is N-channel enhancement; said pulling transistor is a P-channel enhancement transistor; said first current supply terminal is a ground terminal; and said second current supply terminal is a positive power supply terminal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-02-23 | 1990-08-25 | 1991-02-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-02-23 | 1994-08-25 | 1995-02-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-02-23 | 1998-08-25 | 1999-02-24 | $7700.00 | Window Closed / Lapsed |