Low power consuming decoder circuit for a semiconductor memory device

Claim 1

A decoder circuit for a semiconductor memory device having addresses corresponding to the location of data therein, said decoder circuit comprising: power supply means; a logic circuit means comprising a NOR gate for receiving an address signal as the input thereto, an inverter means for receiving the output of said NOR gate, and an output circuit for receiving the output of said NOR gate and the output of said inverter means and for providing an output in response thereto, said output circuit being connected to said power supply means; a load means in said logic circuit means, said load means comprising a first pair of first and second transistors connected in parallel said first and second transistors being connected to said power supply means; and a clock signal generating means for generating a clock signal in response to a variation in the address signal, the clock signal having a specified time duration, said clock signal generating means being connected to said first transistor and said second transistor being connected to the output of said output circuit; wherein said first transistor turns ON for the specified time duration in synchronization with said address signal, and said second transistor turns ON when said logic circuit means is in a selected condition and turns OFF when said logic circuit means is in a non-selected condition.