Decoder circuit using power switch

Abstract

Abstract PURPOSE: To decrease the power consumption by providing MOSFET to receive the control signal and the address decoding signal at the gate respectively in the MOS static memory using no clock and then turning on the MOSFET at the memory selection time and turning off at the non-selection time respectively. CONSTITUTION: MOSFET T 2 WT 7 with address input terminals a 0 Wa 5 connected to the gate plus the inverter comprising MOSFET T 1 and 1st MOSFET T 8 with control signal ϕ connected to the gate are connected between power source VCC and the earth. Furthermore, MOSFET T 11 is installed to receive signal ϕ at the gate, and MOSFET T 12 and T 13 are connected in series to FET T 11 and then connected between V cc and the earth. At the sane time, output terminals A of FET T 2 WT 7 are connected to the gate of FET T 12 , and furthermore to the gate of FET T 10 . Then signal ϕ is set to H-level at the active time and to L-level at the waiting time, and at the same time FET T 8 and T 11 are turned off at the waiting time to cut off the current to be supplied to the memory. COPYRIGHT: (C)1979,JPO&Japio

Inventors

• 👤 Takeshi Saito
• 👤 Tsuneo Ito

Bibliographic Details