US4086500A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Address decoder
Assignee: Toshiba Corp
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Filing: 1976-12-06
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Granted: 1978-04-25
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Expires: 1996-12-06
Abstract
Abstract An address decoder comprises an OR circuit and a NOR circuit, the OR circuit having switching transistors to which decoder inputs and a chip enable signal are applied, a load transistory and a transistor for precharging a common precharge node by the complementary chip enable signal. The output of this OR circuit is applied to the NOR circuit with the complementary chip enable signal, the set-up time of the decoder or the NOR circuit being independent of the number of decoder inputs.
Inventors
- 👤 Yasoji Suzuki
- 👤 Ochii Kiyofumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01735
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
237 words
An address decoder comprising: a chip enable signal line; a complementary chip enable signal line; a common precharge node; a decoder output node; a first power source; a second power source; a plurality of switching MOS transistors each having a first conductivity type and a decoder input, the channels of which are connected in parallel between the chip enable signal line and the common precharge node; first and second MOS transistors having a second conductivity type and connected between the common precharge node and the first power source in parallel, the first MOS transistor being for use as a load transistor and the gate electrode of the second MOS transistor being connected to the complementary chip enable signal line for precharging the common precharge node; third and fourth MOS transistors having the first conductivity type and connected between the second power source and the decoder output node in series, the gate electrode of the third transistor being connected to the complementary chip enable line, the gate electrode of the fourth MOS transistor being connected to the common precharge node; and fifth and sixth MOS transistors having the second conductivity type and connected between the decoder output node and the first power source in parallel, the gate electrode of the fifth MOS transistor being connected to the complementary chip enable signal line and the gate electrode of the sixth MOS transistor being connected to the common precharge node.
Claim 2
Dependent Claim
237 words
An address decoder comprising: a chip enable signal line; a complementary chip enable signal line; a common precharge node; a decoder output node; a first power source; a second power source; a plurality of switching MOS transistors each having a first conductivity type and a decoder input, the channels of which are connected in parallel between the chip enable signal line and the common precharge node; first and second MOS transistors having a second conductivity type and connected between the common precharge node and the first power source in parallel, the first MOS transistor being for use as a load transistor and the gate electrode of the second MOS transistor being connected to the complementary chip enable signal line for precharging the common precharge node; third and fourth MOS transistors having the first conductivity type and connected between the second power source and the decoder output node in series, the gate electrode of the third transistor being connected to the complementary chip enable line, the gate electrode of the fourth MOS transistor being connected to the common precharge node; and fifth and sixth MOS transistors having the second conductivity type and connected between the decoder output node and the first power source in parallel, the gate electrode of the fifth MOS transistor being connected to the complementary chip enable signal line and the gate electrode of the sixth MOS transistor being connected to the common precharge node.
Claim 3
Dependent Claim
38 words
An address decoder as in claim 1 wherein the first conductivity type is P type and the second conductivity type is N type, and the gate electrode of the first transistor is connected to the second power source.
Claim 4
Dependent Claim
39 words
An address decoder as in claim 1 wherein the first conductivity type is N type and the second conductivity type is P type, and the gate electrode of the first MOS transistor is connected to the second power source.
Claim 5
Dependent Claim
23 words
An address decoder as in claim 1 wherein the gate electrode of the first MOS transistor is connected to the decoder output node.
Claim 6
Dependent Claim
35 words
An address decoder as in claim 1 wherein the values of conductance g m of the third and fourth MOS transistors are determined so that these transistors form a driver circuit for the decoder circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-24 | 1981-10-24 | 1982-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-24 | 1985-10-24 | 1986-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-24 | 1989-10-24 | 1990-04-25 | $7700.00 | Window Closed / Lapsed |