US3863230A
Expired / Lapsed
US
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MOS memory decoder circuit
Assignee: Intel Corp
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Filing: 1973-07-18
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Granted: 1975-01-28
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Expires: 1993-07-18
Abstract
Abstract A decoder circuit for a metal-oxide-semiconductor (MOS) memory array which employs a single clock or timing signal is disclosed. Inverter buffers are utilized with a plurality of different decoder logic circuits. Discrimination of each input address is accomplished by the structurally different decoder logic circuits as opposed to the prior art technique of selecting different buffered address inputs.
Inventors
- 👤 William M Regitz
- 👤 John A Reed
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:19
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; H; H03; H03M; H03M7/00
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
138 words
In a decoder for a memory which produces an output signal upon recognition of a predetermined address with a decoder circuit which includes at least two transistors in parallel which receive a portion of said address, and at least two transistors in series which receive the remainder of said address, a circuit for preventing sAid output signal from being produced without receipt by said decoder of said predetermined address, due to electrical charge being stored on said transistors in series comprising: logic circuit means for recognizing a predetermined electrical condition including terminals for receiving said remainder of said address; and, disenabling means for preventing the production of said output signal coupled to said logic circuit means; whereby upon recognition by said logic circuit means of said predetermined electrical condition said decoder is prevented from producing said output signal.
Claim 2
Dependent Claim
138 words
In a decoder for a memory which produces an output signal upon recognition of a predetermined address with a decoder circuit which includes at least two transistors in parallel which receive a portion of said address, and at least two transistors in series which receive the remainder of said address, a circuit for preventing sAid output signal from being produced without receipt by said decoder of said predetermined address, due to electrical charge being stored on said transistors in series comprising: logic circuit means for recognizing a predetermined electrical condition including terminals for receiving said remainder of said address; and, disenabling means for preventing the production of said output signal coupled to said logic circuit means; whereby upon recognition by said logic circuit means of said predetermined electrical condition said decoder is prevented from producing said output signal.
Claim 3
Dependent Claim
18 words
The circuit defined in claim 1 wherein said disenabling means comprises a transistor for discharging an output line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-27 | 1978-07-29 | 1979-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-27 | 1982-07-29 | 1983-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-27 | 1986-07-29 | 1987-01-28 | $7700.00 | Window Closed / Lapsed |