Chip select circuit for multichip random access memory

Claim 2

A random access read-write memory comprising a plurality of units each having a plurality of address stations at which data is adapted to be stored, means for writing new data into a selected one of said address stations on a selected one of said units, means for selecting said one of said units, and means operatively connected between said data writing means and said unit selecting means for inhibiting the output from said writing means to all said units other than said selected one of said units.

Claim 3

The memory of claim 1, in which said units each comprising a chip of semiconductor material, said unit-selecting means comprising means for producing a unique signal for only said selected one of said chips.

Claim 4

The memory of claim 2, in which said writing means comprises means for providing a write command signal at a first level at said selected chip, said inhibiting means comprising means for providing a write inhibit signal at a second level different from said first level at the unselected ones of said chips.

Claim 5

The memory of claim 3, in which said writing means comprises an output terminal, and a line at said second level, said inhibiting means comprising switch means operatively connected between said output terminal and said line and effective when actuated by an inverse unit select signal derived from said unit selecting means to operatively connect the former to the latter.

Claim 6

The memory of claim 4, in which said inhibiting means further comprise second switch means having a control terminal operatively connected to said output teRminal, an intermediate point operatively connected to said control terminal, and third switch means effective when actuated by said inverse unit select signal to operatively connect said intermediate point to said line, thereby to establish an inhibit signal at said control terminal.

Claim 7

The memory of claim 1, in which said writing means comprises means for providing a write signal at a first level at said selected unit, said inhibiting means comprising means for establishing a signal at a second level different from said first level at the selected ones of said units.

Claim 8

The memory of claim 6, in which said writing means comprises an output terminal, and a line at said second level, said inhibiting means comprising switch means operatively connected between said output terminal and said line and effective when actuated by an inverse unit select signal derived from said unit selecting means to operatively connect the former to the latter.

Claim 9

The memory of claim 7, in which said inhibiting means further comprises second switch means having a control terminal, an intermediate point operatively connected to said control terminal, and third switch means effective when actuated by said inverse unit select signal to operatively connect said intermediate point to said line, thereby to establish an inhibit signal at said control terminal.

Claim 10

The memory of claim 1, further comprising a source of timing signals, a source of address station select signals, a source of data signals, a data storage device at each of said address stations, and means for writing data at a selected one of said address stations, said writing means comprising four switch means operatively connected in series between an input point adapted to be operatively connected to the storage device in said selected address station and a reference point, said switch means each having a control terminal to which are respectively applied one of said address station select signals, one of said timing signals, a write command signal from said writing means, and one of said data signals, the first-mentioned two signals being applied to the control terminals of two of said switch means nearest said input point, said last-two-mentioned signals being applied to the control terminals of the two of said switch means nearest said reference point.