US4570084A
Expired / Lapsed
US
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Clocked differential cascode voltage switch logic systems
Assignee: International Business Machines Corp
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Filing: 1983-11-21
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Granted: 1986-02-11
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Expires: 2003-11-21
Abstract
Abstract A differential logic system is provided for a complete logic family which has a first switching circuit that produces a given output signal at a first output node and a second switching circuit that produces a second output signal which is the complement of that of the given output signal at a second output node. First and second clocked devices are connected from the first and second output nodes, respectively, to a voltage source, and first and second inverters are connected to the first and second output nodes, respectively. Additionally, a regenerative circuit may be connected between the first and second output nodes and the voltage source.
Inventors
- 👤 William R. Griffin
- 👤 Lawrence G. Heller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1738
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
164 words
A differential logic system comprising a first switching circuit including input terminals and a first output terminal having a given signal, a second switching circuit including input terminals and a second output terminal having a signal complementary to that of said first output terminal, a voltage source, a first clocked device connected between said voltage source and said first output terminal, a second clocked device connected between said voltage source and said second output terminal, a first inverter circuit having an input terminal connected to said first output terminal and an output terminal for providing an output signal, a second inverter circuit having an input terminal connected to said second output terminal and an output terminal for providing an output signal complementary to that at the output terminal of said first inverter, and means for applying given logic signals to the input terminals of said first switching circuit and for simultaneously applying complementary logic signals to the input terminals of said second switching circuit.
Claim 2
Dependent Claim
164 words
A differential logic system comprising a first switching circuit including input terminals and a first output terminal having a given signal, a second switching circuit including input terminals and a second output terminal having a signal complementary to that of said first output terminal, a voltage source, a first clocked device connected between said voltage source and said first output terminal, a second clocked device connected between said voltage source and said second output terminal, a first inverter circuit having an input terminal connected to said first output terminal and an output terminal for providing an output signal, a second inverter circuit having an input terminal connected to said second output terminal and an output terminal for providing an output signal complementary to that at the output terminal of said first inverter, and means for applying given logic signals to the input terminals of said first switching circuit and for simultaneously applying complementary logic signals to the input terminals of said second switching circuit.
Claim 3
Dependent Claim
39 words
A differential logic system as set forth in claim 1 wherein said clocked devices are P channel devices and further including means for applying clocked pulses simultaneously to the control gates of said first and second P channel devices.
Claim 4
Dependent Claim
39 words
A differential logic system as set forth in claim 1 wherein said clocked devices are N channel devices and further including means for applying clocked pulses simultaneously to the control gates of said first and second N channel devices.
Claim 5
Dependent Claim
49 words
A differential logic system as set for in claim 1 wherein said first and second switching circuits include N channel devices having an enabling device and further including means for applying clocked pulses simultaneously to the control gates of said first and second clocked devices and said enabling device.
Claim 6
Dependent Claim
22 words
A differential logic system as set forth in claim 1 wherein said logic signals applying means includes a differential ended logic network.
Claim 7
Dependent Claim
26 words
A differential logic system as set forth in claim 1 further including regenerative circuits connected between said first and second output terminals and said voltage source.
Claim 8
Dependent Claim
51 words
A differential logic system as set forth in claim 1 further including clocked enabling means connected between each of said first and second switching circuits and a point of reference potential and means for simultaneously applying clocked pulses to said first and second clocked devices and to said clocked enabling means.
Claim 9
Dependent Claim
34 words
A differential logic system as set forth in claim 7 wherein each of said first and second clocked devices includes a P channel transistor and said clocked enabling means includes an N channel transistor.
Claim 10
Dependent Claim
67 words
A differential logic system as set forth in claim 8 further including a first P channel feedback transistor connected in parallel with said first clocked device having a control gate connected to the output terminal of said first inverter and a second P channel feedback transistor connected in parallel with said second clocked device having a control gate connected to the output terminal of said second inverter.
Claim 11
Dependent Claim
29 words
A differential logic system as set forth in claim 7 wherein each of said first and second clocked devices and said clocked enabling means includes an N channel transistor.
Claim 12
Dependent Claim
67 words
A differential logic system as set forth in claim 10 further including a first N channel feedback transistor connected in parallel with said first clocked device having a control gate connected to the output terminal of said second inverter and a second N channel feedback transistor connected in parallel with said second clocked device having a control gate connected to the output terminal of said first inverter.
Claim 13
Dependent Claim
30 words
A differential logic system as set forth in claim 7 further including first and second feedback circuits connected between said first and second output terminals, respectively, and said voltage source.
Claim 14
Dependent Claim
104 words
A differential logic system as set forth in claim 12 wherein said first inverter circuit includes a first P channel transistor and a first N channel transistor serially interconnected between said voltage source and a point of reference potential with the control gates of each of said transistors being connected to said first output terminal, and said second inverter circuit includes a second P channel transistor and a second N channel transistor serially interconnected between said voltage source and said point of reference potential with the control gates of each of said second P and N transistors being connected to said second output terminal.
Claim 15
Dependent Claim
24 words
A differential logic system as set forth in claim 1 wherein each of said first and second switching circuits includes an N channel transistor.
Claim 16
Dependent Claim
142 words
A differential logic system comprising a first switching circuit including input terminals and a first output node having a given signal, a second switching circuit including input terminals and a second output node having a signal complementary to that of said first output node, a first P channel device connected between said first output node and a source of potential, a second P channel device connected between said second output node and said source of potential, a first inverter circuit having an input connected to said first output node and an output terminal, a second inverter circuit having an input connected to said second output node and an output terminal, means for applying clock pulses to said first and second P channel devices, and means for applying differential logic signals simultaneously to the input terminals of said first and second switching circuits.
Claim 17
Dependent Claim
142 words
A differential logic system comprising a first switching circuit including input terminals and a first output node having a given signal, a second switching circuit including input terminals and a second output node having a signal complementary to that of said first output node, a first P channel device connected between said first output node and a source of potential, a second P channel device connected between said second output node and said source of potential, a first inverter circuit having an input connected to said first output node and an output terminal, a second inverter circuit having an input connected to said second output node and an output terminal, means for applying clock pulses to said first and second P channel devices, and means for applying differential logic signals simultaneously to the input terminals of said first and second switching circuits.
Claim 18
Dependent Claim
69 words
A differential logic system as set forth in claim 15 further including a first P channel feedback transistor connected in parallel with said first P channel device having a control gate connected to the output terminal of said first inverter and a second P channel feedback transistor connected in parallel with said second P channel device having a control gate connected to the output terminal of said second inverter.
Claim 19
Dependent Claim
130 words
A differential logic system comprising a logic network having inputs for receiving differential input signals and first and second output nodes for providing complementary output signals, a voltage source, a first clocked device connected between said first output node and said voltage source, a second clocked device connected between said second output node and said voltage source, clocked enabling means connected between a point of reference potential and said first and second output nodes through said logic network, means for applying clock pulses to said first and second clocked devices and said clocked enabling means, a first inverter circuit having an input connected to said first output node and an output terminal, and a second inverter circuit having an input connected to said second output node and an output terminal.
Claim 20
Dependent Claim
130 words
A differential logic system comprising a logic network having inputs for receiving differential input signals and first and second output nodes for providing complementary output signals, a voltage source, a first clocked device connected between said first output node and said voltage source, a second clocked device connected between said second output node and said voltage source, clocked enabling means connected between a point of reference potential and said first and second output nodes through said logic network, means for applying clock pulses to said first and second clocked devices and said clocked enabling means, a first inverter circuit having an input connected to said first output node and an output terminal, and a second inverter circuit having an input connected to said second output node and an output terminal.
Claim 21
Dependent Claim
65 words
A differential logic system as set forth in claim 17 further including a first feedback transistor connected in parallel with said first clocked device and having a control gate connected to the output terminal of said first inverter and a second feedback transistor connected in parallel with said second clocked device and having a control gate connected to the output terminal of said second inverter.
Claim 22
Dependent Claim
118 words
A differential logic circuit comprising an exclusive OR logic network having input terminals for receiving differential logic input signals and first and second output nodes for providing complementary output signals, clocked means for enabling said network, a voltage source, a first clocked device connected between said first output node and said voltage source, a second clocked device connected between said second output node and said voltage source, means for applying clock pulses to said clocked means and said first and second clocked devices, a first inverter having an input terminal connected to said first output node and an output terminal, and a second inverter having an input terminal connected to said second output node and an output terminal.
Claim 23
Dependent Claim
118 words
A differential logic circuit comprising an exclusive OR logic network having input terminals for receiving differential logic input signals and first and second output nodes for providing complementary output signals, clocked means for enabling said network, a voltage source, a first clocked device connected between said first output node and said voltage source, a second clocked device connected between said second output node and said voltage source, means for applying clock pulses to said clocked means and said first and second clocked devices, a first inverter having an input terminal connected to said first output node and an output terminal, and a second inverter having an input terminal connected to said second output node and an output terminal.
Claim 24
Dependent Claim
34 words
A differential logic system as set forth in claim 19 wherein said exclusive OR network and said clocked means include N channel transistors and said first and second clocked devices include P channel transistors.
Claim 25
Dependent Claim
57 words
A differential logic system as set forth in claim 19 further including a first feedback transistor connected in parallel with said first clocked device and controlled by the output terminal of said first inverter and a second feedback transistor connected in parallel with said second clocked device and controlled by the output terminal of said second inverter.
Claim 26
Dependent Claim
153 words
A differential logic system comprising a first switching circuit arranged in the form of an exclusive OR circuit including N channel transistors, input terminals and a first output terminal having a given signal, a second switching circuit arranged in the form of an exclusive OR circuit including N channel transistors, input terminals and a second output terminal having a signal complementary to that of said first output terminal, a voltage source, a first clocked device connected between said voltage source and said first output terminal, a second clocked device connected between said voltage source and said second output terminal, a first inverter circuit having an output terminal and an input terminal connected to said first output terminal, a second inverter circuit having an output terminal and an input terminal connected to said second output terminal, and means for applying logic signals simultaneously to the input terminals of said first and second switching circuits.
Claim 27
Dependent Claim
153 words
A differential logic system comprising a first switching circuit arranged in the form of an exclusive OR circuit including N channel transistors, input terminals and a first output terminal having a given signal, a second switching circuit arranged in the form of an exclusive OR circuit including N channel transistors, input terminals and a second output terminal having a signal complementary to that of said first output terminal, a voltage source, a first clocked device connected between said voltage source and said first output terminal, a second clocked device connected between said voltage source and said second output terminal, a first inverter circuit having an output terminal and an input terminal connected to said first output terminal, a second inverter circuit having an output terminal and an input terminal connected to said second output terminal, and means for applying logic signals simultaneously to the input terminals of said first and second switching circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-10 | 1989-08-12 | 1990-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-10 | 1993-08-12 | 1994-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-10 | 1997-08-12 | 1998-02-11 | $7700.00 | Window Closed / Lapsed |